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參數(shù)資料
| 型號(hào)： | PCL6045B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | User Manual For PCL6045B Pulse Control LSI |
| 中文描述： | 用戶手冊(cè)PCL6045B脈沖控制大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 163/176頁(yè) |
| 文件大?。?/td> | 7952K |
| 代理商： | PCL6045B |
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156
-
Label
Type
Position
RIPS
4
RIPS
5
RIPS
6
RIPS
15
RIPS
12
RIPS
13
RIPS
14
RIPS
16
RIPS
3
RIPS
0
RIPS
1
RIPS
2
RIPS
11
RIPS
8
RIPS
9
RIPS
10
RIRQ
8
RIRQ
9
RIRQ
10
RIRQ
11
RIRQ
12
RIRQ
13
RIRQ
7
RIRQ
17
RIRQ
6
RIRQ
0
RIRQ
14
RIRQ
1
RIRQ
3
RIRQ
2
RIRQ
15
RIRQ
18
RIRQ
16
RIRQ
5
RIRQ
4
RIST
8
RIST
9
RIST
10
RIST
11
RIST
12
RIST
13
RIST
7
RIST
6
RIST
0
RIST
14
RIST
18
RIST
1
RIST
3
RIST
2
RIST
15
RIST
17
RIST
19
RIST
16
RIST
5
RIST
4
Description
Reference
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P54
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P48,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
P52,137
IPEx
IPEy
IPEz
IPFu
IPFx
IPFy
IPFz
IPL
IPLu
IPLx
IPLy
IPLz
IPSu
IPSx
IPSy
IPSz
IRC1
IRC2
IRC3
IRC4
IRC5
IRCL
IRDE
IRDR
IRDS
IREN
IRLT
IRN
IRND
IRNM
IROL
IRSA
IRSD
IRUE
IRUS
ISC1
ISC2
ISC3
ISC4
ISC5
ISCL
ISDE
ISDS
ISEN
ISLT
ISMD
ISN
ISND
ISNM
ISOL
ISPD
ISSA
ISSD
ISUE
ISUS
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
Register
bit
X
axis
linear
interpolation
mode
from
a
specified
master
axis
feed
amount
Y
axis
linear
interpolation
mode
from
a
specified
master
axis
feed
amount
Z
axis
linear
interpolation
mode
from
a
specified
master
axis
feed
amount
Specify
a
synthetic
constant
speed
for
the
U
axis
Specify
a
synthetic
constant
speed
for
the
X
axis
Specify
synthetic
constant
speed
for
the
Y
axis
Specify
a
synthetic
constant
speed
for
the
Z
axis
Executing
a
normal
linear
interpolation
U
axis
is
in
normal
linear
interpolation
mode
X
axis
is
in
normal
linear
interpolation
mode
Y
axis
is
in
normal
linear
interpolation
mode
Z
axis
is
in
normal
linear
interpolation
mode
U
axis
is
in
circular
interpolation
mode
X
axis
is
in
circular
interpolation
mode
Y
axis
is
in
circular
interpolation
mode
Z
axis
is
in
circular
interpolation
mode
Enable
an
INT
when
the
comparator1
conditions
are
met
Enable
an
INT
when
the
comparator2
conditions
are
met
Enable
an
INT
when
the
comparator3
conditions
are
met
Enable
an
INT
when
the
comparator4
conditions
are
met
Enable
an
INT
when
the
comparator5
conditions
are
met
Enable
an
INT
when
the
count
value
is
reset
by
a
CLR
input
Enable
an
INT
when
the
deceleration
is
finished
Enable
an
INT
when
the
±DR
input
changes
Enable
an
INT
when
the
deceleration
starts
Enable
an
INT
when
there
is
a
normal
stop
Enable
an
INT
when
the
count
value
is
latched
by
an
LTC
input
Enable
INT
by
continuing
with
the
next
operation.
Enable
an
INT
when
writing
to
the
2nd
pre-register
for
comparator5
is
enabled
Enable
an
INT
when
writing
to
2nd
pre-register
for
operation
is
enabled
Enable
an
INT
when
the
count
value
is
latched
by
an
ORG
input
Enable
an
INT
by
turning
ON
the
input
Enable
an
INT
by
turning
ON
the
SD
input
Enable
an
INT
when
the
acceleration
is
finished
Enable
an
INT
when
acceleration
starts
Comparator
1
conditioned
status
Comparator
2
conditioned
status
Comparator
3
conditioned
status
Comparator
4
conditioned
status
Comparator
5
conditioned
status
Reset
the
count
value
when
a
CLR
signal
is
input
Equals
1
when
deceleration
is
finished
Equals
1
when
deceleration
starts
Equals
1
when
stopped
automatically
Equals
1
when
the
count
value
is
latched
by
an
LTC
input
Equals
1
when
a
DR
input
signal
is
input.
To
start
the
next
operation
continuously.
Enable
writing
to
the
2nd
pre-register
for
comparator5
Enable
writing
to
the
2nd
pre-register
for
operations
Latched
count
value
from
the
ORG
input
Equals
1
when
the
+DR
input
is
ON
Equals
1
when
the
CSTA
input
is
ON
Equals
1
when
the
SD
input
is
ON
Equals
1
when
the
acceleration
is
finished
Equals
1
when
to
start
acceleration
LTCH
LTCL
LTCu
LTCx
LTCy
LTCz
LTFD
LTM0
to
1
LTOF
Command
Register
bit
Terminal
name
Terminal
name
Terminal
name
Terminal
name
Register
bit
Register
bits
Register
bit
29h
RENV1
23
152
51
87
115
RENV5
14
RENV5
12-13
RENV5
15
Substitute
the
LTC
input
(for
counting
or
latching)
Select
the
trigger
edge
for
the
LTC
signal
(0:
Falling
edge,
1:
Rising
edge)
Latch
the
input
for
the
U
axis
Latch
the
input
for
the
X
axis
Latch
the
input
for
the
Y
axis
Latch
the
input
for
the
Z
axis
Latch
the
current
speed
data
in
place
of
COUNTER3
Specify
the
latch
timing
of
COUNTERS
1
to
4
Stop
the
latch
using
hardware
timing
P24,
116
P37,
116
P10,
116
P10,
116
P10,
116
P10,
116
P44,
116
P44,
116
P44,
116
MADJ
MAX0
to
3
MCCE
Register
bit
Register
bits
Register
bit
RMD
26
RMD
20-21
RMD
11
Disable
the
FH
correction
function
Specify
the
axis
used
to
control
stopping
for
a
simultaneous
start
Stop
the
operation
of
COUNTER1
(command
position)
Does
not
output
a
stop
INT
between
blocks
while
in
continuous
operation
using
the
pre-
register.
Select
the
operation
completion
timing
(0:
Stop
at
the
end
of
a
cycle,
1:
Stop
on
a
pulse)
The
operation
is
complete
when
the
INP
input
turns
ON
P34
P34,
128
P34,
117
MENI
Register
bit
RMD
7
P34,
136
METM
Register
bit
RMD
12
P34,
100
MINP
Register
bit
RMD
9
P34,
106
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