參數(shù)資料
型號： PCL6045B
廠商： Electronic Theatre Controls, Inc.
英文描述： User Manual For PCL6045B Pulse Control LSI
中文描述： 用戶手冊PCL6045B脈沖控制大規(guī)模集成電路
文件頁數(shù)： 107/176頁
文件大?。?/td> 7952K
代理商： PCL6045B
-
100
-
11-3-2.
Control
the
output
pulse
width
and
operation
complete
timing
In
order
to
increase
the
stopping
speed,
this
LSI
controls
the
output
pulse
width.
When
the
output
pulse
speed
is
slower
than
1/8192
of
reference
clock
(approx.
2.4
Kpps
when
CLK
=
19.6608
MHz),
the
pulse
width
is
constant
and
is
4096
cycles
of
the
reference
clock
(approx.
200
μsec
when
CLK
=
19.6608
MHz).
For
faster
pulse
speeds
than
this,
the
duty
cycle
is
kept
constant
(approx.
50%).
By
setting
PDTC
(bit
13)
in
the
RENV1
register
(environment
setting
1),
the
output
pulse
width
can
be
set
to
make
a
constant
duty
cycle
(50%).
Also,
when
setting
METM
(operation
completion
timing
setting)
in
the
PRMD
register
(operation
mode),
the
operation
complete
timing
can
be
changed.
1)
When
METM
=
0
(the
point
at
which
the
output
frequency
cycle
is
complete)
in
the
PRMD
register
2)
When
METM
=
1
(when
the
output
pulse
is
OFF)
in
the
PRMD
register
When
set
to
"complete
when
the
output
pulse
is
OFF,"
the
time
interval
"Min"
from
the
last
pulse
until
the
next
starting
pulse
output
will
be
T
MIN
=
15
x
T
CLK
.
(T
CLK
:
Reference
clock
frequency)
Setting
the
operation
complete
timing
<Set
METM
(bit
12)
in
PRMD>
0:
At
the
end
of
a
cycle
of
a
particular
output
frequency
1:
Complete
when
the
output
pulse
turns
OFF.
Setting
the
output
pulse
width
<Set
PDTC
(bit
31)
in
RENV1>
0:
Automatically
change
between
a
constant
output
pulse
and
a
constant
duty
cycle
(approx.
50%)
in
accord
with
variations
in
speed.
1:
Keep
the
output
pulse
width
at
a
constant
duty
cycle
(approx.
50%).
[RMD]
(WRITE)
15
n
- - -
8
- - - -
[RENV1]
(WRITE)
31
n
-
-
-
-
-
-
-
24
Output
pulse
frequency
BSY
OUT
Last
pulse
10xT
CLK
1st
pulse
of
the
next
operation
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