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參數(shù)資料
| 型號(hào)： | PCL6045B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | User Manual For PCL6045B Pulse Control LSI |
| 中文描述： | 用戶手冊(cè)PCL6045B脈沖控制大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 14/176頁(yè) |
| 文件大?。?/td> | 7952K |
| 代理商： | PCL6045B |
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- 7 -
CPU signal connected to the
terminal
IF1 IF0
CPU
example
A0
L
L
H
H
L
H
L
H
68000
H8
8086
Z80
+5 V
R/
(GND)
(GND) READY
A0
4. Functions of Terminals
Signal name
Terminal
No.
17, 25,
39, 56,
77, 105,
127,
163, 176
33, 61,
100,121,
149,
161,
162,165,
166,167
12, 88,
144
Input/
output
Power
source
Logic
Description
GND
Supply a negative power.
Make sure to connect all of these terminals.
VDD5
Power
source
Supply +5 VDC power.
The allowable power supply range is +5 VDC ±10%.
Make sure to connect all of these terminals.
VDD3
Power
source
Supply +3.3 VDC power.
The allowable power supply range is +3.3 VDC ±10%.
Make sure to connect all of these terminals.
Negative Input reset signal.
Make sure to set this signal LOW after turning ON the power and
before starting operation. Input and holding
8 cycles of the reference clock.
For details about the chip's status after a reset, see section 11-1,
"Reset", in this manual.
Input a CMOS level reference clock signal.
(Signals other than the CLK are TTL level inputs.)
The reference clock frequency is 19.6608 MHz. The LSI creates
output pulses based on the clock input on this terminal.
Enter the CPU-I/F mode
175
Input
low for at least
CLK
164
Input
IF0
IF1
1
2
Input
3
Input
Negative When the signal level on this terminal is LOW, the
terminals will be valid.
Negative Connect the I/F signals to the CPU. The
are valid when
terminal is LOW.
Positive Address control signals
and
4
5
6 to 10
Input
and
terminals
A0 to A3
Input
11
Input
Negative Outputs an interrupt request signal (IRQ) to an external CPU.
After this terminal is turned ON, the signal will return to OFF
when a RESET (error interrupt cause) or RIST (event interrupt
cause) signal is received. The output status can be checked with
an MSTSW (main status) command signal.
The
signal can be masked.
When more than one 6045B LSI is used, a wired OR connection
between
terminals is not allowed.
Output Negative Outputs a wait request signal to cause a CPU to wait.
The LSI needs 4 reference clock cycles to process each
command. If the
signal is not used, make sure that an
external CPU does not access this LSI during this interval.
13
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