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參數(shù)資料
| 型號(hào)： | PCL6045B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | User Manual For PCL6045B Pulse Control LSI |
| 中文描述： | 用戶手冊(cè)PCL6045B脈沖控制大規(guī)模集成電路 |
| 文件頁(yè)數(shù)： | 111/176頁(yè) |
| 文件大?。?/td> | 7952K |
| 代理商： | PCL6045B |
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-
104
-
4)
Latched,
deceleration
stop
<SDM
(bit
4)
=
1,
SDLT
(bit
5)=1
in
RENV1>
-
If
the
SD
signal
is
turned
ON
while
in
low
speed
operation,
the
axis
will
stop.
If
the
SD
signal
is
turned
ON
while
in
high
speed
operation,
the
axis
will
decelerate
to
FL
speed
and
then
stop.
Even
if
the
SD
signal
is
turned
OFF
during
deceleration,
the
axis
will
not
accelerate.
-
If
the
SD
signal
is
turned
ON
while
writing
a
start
command,
the
axis
will
not
start
moving
and
the
operation
will
not
be
completed.
-
While
stopped,
the
LSI
outputs
an
signal.
[FL
low
speed
operation]
[FH
low
speed
operation]
[High
speed
operation]
The
input
logic
of
the
SD
signal
can
be
changed.
If
the
latched
input
is
set
to
accept
input
from
the
SD
signal,
and
if
the
SD
signal
is
OFF
at
the
next
start,
the
latch
will
be
reset.
The
latch
is
also
reset
when
the
latch
input
is
set
to
zero.
The
minimum
pulse
width
of
the
SD
signal
is
80
reference
clock
cycles
(4.0
μsec)
when
the
input
filter
is
ON.
When
the
input
filter
is
turned
OFF,
the
minimum
pulse
width
is
two
reference
clock
cycles
(0.1
μsec).
(When
CLK
=
19.6608
MHz.)
The
latch
signal
of
the
SD
signal
can
be
monitored
by
reading
SSTSW
(sub
status).
The
SD
signal
terminal
status
can
be
monitored
by
reading
RSTS
(extension
status).
By
reading
the
REST
register,
you
can
check
for
an
error
interrupt
caused
by
the
SD
signal
turning
ON.
Enable/disable
SD
signal
input
<Set
MSDE
(bit
8)
in
PRMD>
0:
Enable
SD
signal
input
1:
Disable
SD
signal
input
[RMD]
(WRITE)
15
-
-
-
-
-
-
-
n
[RENV1]
(WRITE)
7
-
n
-
-
-
-
-
-
8
Input
logic
of
the
SD
signal
<Set
SDL(bit
6)
in
RENV1>
0:
Negative
logic
1:
Positive
logic
[RENV1]
(WRITE)
7
-
-
-
n
-
-
-
-
0
Set
the
operation
pattern
when
the
SD
signal
is
turned
ON
<Set
SDM
(bit
4)
in
RENV1>
0:
Decelerates
on
receiving
the
SD
signal
and
feeds
at
FL
low
speed
1:
Decelerates
and
stops
on
receiving
the
SD
signal
Select
the
SD
signal
input
type
<Set
SDLT
(bit
5)
in
RENV1>
0:
Level
input
1:
Latch
input
To
release
the
latch,
turn
OFF
the
SD
input
when
next
start
command
is
written
or
select
Level
input.
Reading
the
latch
status
of
the
SD
signal
<SSD
(bit
15)
in
SSTSW>
0:
The
SD
latch
signal
is
OFF
1:
The
SD
latch
signal
is
ON
0
[RENV1]
(WRITE)
7
-
-
n
-
-
-
-
-
0
[SSTSW]
(READ)
15
n
-
-
-
-
-
-
-
[RSTS]
(READ)
15
n
-
-
-
-
-
-
-
8
Reading
the
SD
signal
<
SDIN
(bit
15)
in
the
RSTS
register>
0:
The
SD
signal
is
OFF
1:
The
SD
signal
is
ON
[REST]
(READ)
15
-
-
-
-
0
n
-
-
8
Reading
the
cause
of
an
RESET>
1:
Deceleration
stop
caused
by
the
SD
signal
turning
ON
when
stopped
by
the
SD
signal
<ESSD
(bit
10)
in
[RENV1]
(WRITE)
31
-
-
-
-
-
n
-
-
8
Apply
an
input
filter
to
SD
<Set
FLTR
(bit
26)
in
RENV1>
1:
Apply
a
filter
to
the
SD
input
By
applying
a
filter,
signals
with
a
pulse
width
of
4
μsec
or
less
will
be
ignored.
24
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