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參數(shù)資料
| 型號(hào)： | PCI9060 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 83/192頁(yè) |
| 文件大小： | 1551K |
| 代理商： | PCI9060 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 74
Version 1.02
4.5.11 (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register
Field
Description
Read
Write
Value after Reset
0
Enable Local Bus LSERR#. Value of 1 enables PCI 9080 to assert LSERR#
interrupt output when PCI bus Target Abort or Master Abort status bit is set in the
PCI Status configuration register.
Yes
Yes
0
1
Enable Local Bus LSERR# when PCI parity error occurs during PCI 9080 Master
Transfer or PCI 9080 Slave access or Outbound Free List FIFO Overflow Init.
Yes
Yes
0
2
Generate PCI Bus SERR#. When this bit is set to 0, writing a 1 generates a PCI
bus SERR#.
Yes
Yes
0
3
Mailbox Interrupt Enable. Value of 1 enables a Local Interrupt to be generated
when the PCI bus writes to Mailbox registers 0-3. To clear the Local Interrupt, the
Local master must read the Mailbox. Used in conjunction with Local interrupt
enable.
Yes
Yes
0
7:4
Reserved.
Yes
No
0
8
PCI Interrupt Enable. Value of 1 enables PCI interrupts.
Yes
Yes
1
9
PCI Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in
conjunction with PCI interrupt enable. Clearing the doorbell interrupt bits that
caused the interrupt also clears the interrupt.
Yes
Yes
0
10
PCI Abort Interrupt Enable. Value of 1 enables a master abort or master detect of a
target abort to generate a PCI interrupt. Used in conjunction with PCI interrupt
enable. Clearing the abort status bits also clears the PCI interrupt.
Yes
Yes
0
11
PCI Local Interrupt Enable. Value of 1 enables a local interrupt input to generate a
PCI interrupt. Use in conjunction with PCI interrupt enable. Clearing the local bus
cause of the interrupt also clears the interrupt.
Yes
Yes
0
12
Retry Abort Enable. Value of 1 enables PCI 9080 to treat 256 Master consecutive
retries to a Target as a Target Abort. Value of 0 enables PCI 9080 to attempt
Master Retries indefinitely.
Note:
For diagnostic purposes only.
Yes
Yes
0
13
Value of 1 indicates PCI doorbell interrupt is active.
Yes
No
0
14
Value of 1 indicates PCI abort interrupt is active.
Yes
No
0
15
Value of 1 indicates local interrupt is active (LINTi#).
Yes
No
0
16
Local Interrupt Output Enable. Value of 1 enables local interrupt output.
Yes
Yes
1
17
Local Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in
conjunction with Local interrupt enable. Clearing the local doorbell interrupt bits that
caused the interrupt also clears the interrupt.
Yes
Yes
0
18
Local DMA Channel 0 Interrupt Enable. Value of 1 enables DMA Channel 0
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status
bits also clears the interrupt.
Yes
Yes
0
19
Local DMA Channel 1 Interrupt Enable. Value of 1 enables DMA Channel 1
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status
bits also clears the interrupt.
Yes
Yes
0
20
Value of 1 indicates local doorbell interrupt is active.
Yes
No
0
21
Value of 1 indicates DMA Ch 0 interrupt is active.
Yes
No
0
22
Value of 1 indicates DMA Ch 1 interrupt is active.
Yes
No
0
23
Value of 1 indicates BIST interrupt is active.
BIST (Built-In Self Test) interrupt is generated by writing 1 to bit 6 of the PCI
Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the BIST
Register for a description of self test. (Refer to Table 4-18.)
Yes
No
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI9080 | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ES | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI90603A | 制造商:PLX Technology 功能描述: |
| PCI9060-3A | 制造商:PLX Technology 功能描述: |
| PCI9060-3AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
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