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參數(shù)資料
| 型號： | PCI9060 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁數(shù)： | 18/192頁 |
| 文件大小： | 1551K |
| 代理商： | PCI9060 |
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SECTION 2
PCI 9080
BUS OPERATION
PLX Technology, Inc., 1997
Page 9
Version 1.02
2.2.3.2.3 Partial Lword Accesses
Lword accesses in which not all byte enables are
asserted are broken into single address and data cycles,
as listed in Table 2-9.
Table 2-9. Partial Lword Accesses
Register Value (PCI:18h)(LOC:98h)
Burst Enable
Bterm Enable
Result
(Number of Transfers)
0
0
Single Cycle (Default)
0
1
Single Cycle
1
0
Burst four Lwords at a time
1
1
Continuous Burst Mode
2.2.3.3 Recovery States
In J and S modes, PCI 9080 inserts one recovery state
between the last data transfer and next address cycle.
PCI 9080 does not support the 80960J feature of using
READYi# input to add recovery states. No additional
recovery states are added if READYi# input remains
asserted during the last data cycle.
2.2.3.4 Local Bus Read Accesses
For all single cycle local bus read accesses, PCI 9080
reads only bytes corresponding to byte enables
requested by the PCI initiator. For all burst cycle single
cycle bus read accesses, PCI 9080 reads only Lwords.
2.2.3.5 Local Bus Write Accesses
For local bus writes, only the bytes specified by a PCI
bus master or PCI 9080 DMA controller are written.
Access to an 8- or 16-bit bus results in the PCI bus
Lword being broken into multiple local bus transfers. For
each transfer, the byte enables are encoded as in the
80960C to provide local address bits LA[1:0].
2.2.3.6 Direct Slave Write Accesses—8- and
16-Bit Buses
A Direct PCI access to an 8- or 16-bit bus results in the
PCI bus Lword being broken into multiple local bus
transfers. For each transfer, the byte enables are
encoded as in the 80960C to provide local address bits
LA[1:0].
2.2.3.7 Local Bus Data Parity
There is one data parity pin for each byte lane of the PCI
9080 data bus (DP[3:0]). Even data parity is generated
for each lane during local bus reads from PCI 9080 and
during PCI 9080 master writes to the local bus.
Even data parity is checked during local bus writes to
PCI 9080 and during PCI 9080 reads from the local bus.
Parity is checked for each byte lane with an asserted
byte enable. PCHK# is asserted in the clock cycle
following the data being checked if a parity error is
detected.
Generation or use of local bus data parity is optional.
The signals on data parity pins do not effect operation of
PCI 9080. PCI bus parity checking and generation is
independent of local bus parity checking and generation.
2.2.3.8 Local Bus Little/Big Endian
PCI bus is a Little Endian bus (that is, data is Lword
aligned to the lowermost byte lane). Byte 0 (address 0)
appears in AD[7:0], Byte 1 appears in AD[15:8], Byte 2
appears in AD[23:16] and Byte 3 appears in AD[31:24].
PCI 9080 local bus can be programmed to operate in Big
or Little Endian mode, as listed in Table 2-10.
Table 2-10. Big / Little Endian Program Mode
BIGEND# Pin
Register
1=Big, 0=Little
Endian
0
0
Big
0
1
Big
1
0
Little
1
1
Big
For Configuration cycles, refer to Table 4-36[0]. For
Direct Master, Memory, and I/O cycles, refer to Table 4-
36[1]. For Direct Slave cycles, refer to Table 4-36[2],
Space 0, and Table 4-36[3], expansion ROM.
In Big Endian mode, PCI 9080 transposes the data byte
lanes. Data is transferred as listed in Table 2-11 through
Table 2-15.
2.2.3.8.1 32 Bit Local Bus—Big Endian Mode
Data is Lword aligned to the uppermost byte lane. Byte
lanes and burst orders are listed in Table 2-11 and
illustrated in Figure 2-2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI9080 | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ES | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI90603A | 制造商:PLX Technology 功能描述: |
| PCI9060-3A | 制造商:PLX Technology 功能描述: |
| PCI9060-3AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
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