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參數(shù)資料
| 型號： | PCI9656-AC66BI |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 312K |
| 代理商： | PCI9656-AC66BI |
PCI 9656
64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
PowerQUICC
& Generic 32-bit, 66MHz Local Bus Design
s
Maximum PCI Bandwidth for Your 32-bit Local Bus Applications
The PCI 9656 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
Motorola
MPC 850/860 PowerQUICC Designs
The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection
to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its
Data Pipe Architecture technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-
ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.
The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI
I/O with those devices.
Move Your 32-bit Local Bus Designs Up to
64-bit, 66MHz PCI Operation
As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX
continues to provide leading edge, high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of
enhancements for the needs of today's telecom, networking, and I/O adapter designs:
I
64-bit, 66MHz PCI operation
I
32-bit, 66MHz local bus operation
I
Dynamic DMA descriptor ring management with Valid bit semaphore control
I
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit
Initialization, and Intially Not Responding Support
I
PCI Power Management r1.1 D3
COLD
Power Management Event (PME) generation
I
PCI arbiter supporting 7 external masters
I
Reset and interrupt pins configurable for embedded host applications
I
JTAG boundary scan
The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.
Connectivity
I
64-bit, 66MHz PCI r2.2 compliant
I
Motorola PowerQUICC and
generic 32-bit, 66MHz local
bus modes
I
3.3V I/O, 5V tolerant bus
interfaces
I
PICMG 2.1 r2.0 Hot Swap Silicon
I
272-ball, 27 x 27 mm, 1.27 mm
pitch PBGA
Performance
I
Zero wait state burst operation
–
PCI bus bursts to 528 MB/sec
–
Local bus bursts to 264 MB/sec
I
2 DMA Channels
–
Block and Scatter/Gather transfers
–
DMA descriptor ring management
–
Demand Mode and EOT
Hardware controls
I
Direct Master data transfers
–
Generate any PCI transaction
–
Read ahead and programmable
read prefetch counter
I
Direct Slave data transfers
–
Access 8-, 16-, and 32-bit local
bus devices
–
Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
Control
I
I2O r1.5 messaging unit
I
Eight mailbox and two
doorbell registers
I
PCI arbiter supports 7
external masters
I
Host mode reset/interrupt signal
configuration
I
PCI D3
COLD
Power Management
Event (PME) generation support
I
Serial EEPROM interface
I
JTAG boundary scan
V E R S I O N 1 . 0
2 0 0 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9656-BA66BI | 功能描述:外圍驅(qū)動器與原件 - PCI 64-bit 66MHz PCI Bus Mastering I/O RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9656-BA66BI G | 制造商:PLX Technology 功能描述:IC PCI BUS MASTER BRIDGE 272PBGA |
| PCI9656-BA66BIG | 制造商:PLX 制造商全稱:PLX 功能描述:64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC⑩ & Generic 32-bit, 66MHz Local Bus Designs |
| PCI9656-BA66BI-G | 功能描述:外圍驅(qū)動器與原件 - PCI 64-bit 66MHz PCI Bus Mastering I/O RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI9656RDK-LITE | 功能描述:界面開發(fā)工具 PCI9656 KIT RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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