參數(shù)資料
型號(hào): PCI6515GHK
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述: 單插槽CardBus控制器,專用智能卡插槽
文件頁(yè)數(shù): 78/148頁(yè)
文件大?。?/td> 760K
代理商: PCI6515GHK
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420
4.30 General Control Register
The general control register provides top level PCI arbitration control. It also provides control over miscellaneous new
functionality. See Table 49 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
General control
Type
RW
RWU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Register:
Offset:
Type:
Default:
General control
86h
Read/Write, Read-only
0003h
Table 49. General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
15
RSVD
RW
Reserved, this bit has no effect on device operation.
14
SC_IF_SEL
RWU
Smart Card interface select. This bit controls the selection of the dedicated Smart Card interface
used by the controller.
0 = EMV interface selected (default)
1 = PCI6x11-style interface selected
13
RSVD
RW
Reserved.
12
IO_LIMIT_SEL
RW
When this bit is set, bit 0 in the I/O limit registers (PCI offsets 30h and 38h) is set.
0 = Bit 0 in the I/O limit registers is 0 (default)
1 = Bit 0 in the I/O limit registers is 1
11
IO_BASE_SEL
RW
When this bit is set, bit 0 in the I/O base registers (PCI offsets 2Ch and 34h) is set.
0 = Bit 0 in the I/O base registers is 0 (default)
1 = Bit 0 in the I/O base registers is 1
10
12V_SW_SEL
RW
Power switch select. This bit selects which power switch is implemented in the system.
0 = A 1.8-V capable power switch (TPS2228) is used (default)
1 = A 12-V capable power switch (TPS2226) is used
98
RSVD
RW
Reserved, these bits have no effect on device operation.
7
DISABLE_SC
RW
When this bit is set, the Smart Card function is completely nonaccessible and nonfunctional.
63
RSVD
RW
Reserved.
2
RSVD
RW
Reserved.
10
ARB_CTRL
RW
Controls top level PCI arbitration:
00 = 1394 OHCI priority
01 = CardBus priority
10 = Reserved
11 = Fair round robin
One or more bits in this register are cleared only by the assertion of GRST.
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