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| 型號(hào)： | PCI6515GHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專用智能卡插槽 |
| 文件頁(yè)數(shù)： | 36/148頁(yè) |
| 文件大?。?/td> | 760K |
| 代理商： | PCI6515GHK |
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32
Tied for Open Drain
OE
Pad
VCCP
Figure 32. 3-State Bidirectional Buffer
3.3
Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI6515 controller is interfaced with:
3.3 V or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply is 1.5 V and is independent of the clamping voltages. For example, PCI signaling can
be either 3.3 V or 5 V, and the PCI6515 controller must reliably accommodate both voltage levels. This is
accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system
designer desires a 5-V PCI bus, then V
CCP
can be connected to a 5-V power supply.
3.4
Peripheral Component Interconnect (PCI) Interface
The PCI6515 controller is fully compliant with the
PCI Local Bus Specification
. The PCI6515 controller provides all
required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment
by connecting the V
CCP
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI6515
controller provides the optional interrupt signals INTA, INTB, INTC, and INTD.
3.4.1
Device Resets
During the power-up sequence, GRST and PRST must be asserted. GRST is deasserted a minimum of 2 ms after
V
CC
is stable. PRST is deasserted 100
μ
s after PCLK is stable or any time thereafter.
3.4.2
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the
PCI Local Bus Specification
is not highly recommended, but is provided on
the PCI6515 controller as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4
terminal by setting the appropriate values in bits 1916 of the multifunction routing status register. See Section 4.35,
Multifunction Routing Status Register
,
for details. Note that the use of LOCK is only supported by PCI-to-CardBus
bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not assure control of LOCK; control of LOCK is obtained under its own protocol. It is possible for
different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal
for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the
PCI Local Bus Specification
allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter does not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A
complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete
bus LOCK must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked
operation is in progress.
The PCI6515 controller supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve
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