參數(shù)資料
型號(hào)： PCI6515GHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 114/148頁
文件大?。?/td> 760K
代理商： PCI6515GHK
520
5.20 ExCA Global Control Register
This register controls the PC Card socket. The host interrupt mode bits in this register are retained for 82365SL-DF
compatibility. See Table 515 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA global control
Type
R
R
R
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA global control
CardBus Socket Address + 81Eh:
Read-only, Read/Write
00h
Card A ExCA Offset 1Eh
Table 515. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
75
RSVD
R
These bits return 0s when read. Writes have no effect.
4
INTMODEB
RW
Level/edge interrupt mode select, card B. This bit selects the signaling mode for the PCI6515 host interrupt
for card B interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
3
INTMODEA
RW
Level/edge interrupt mode select, card A. This bit selects the signaling mode for the PCI6515 host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
2
IFCMODE
RW
Interrupt flag clear mode select. This bit selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register. This bit is encoded as:
0 = Interrupt flags cleared by read of CSC register (default)
1 = Interrupt flags cleared by explicit writeback of 1
1
CSCMODE
RW
Card status change level/edge mode select. This bit selects the signaling mode for the PCI6515 host
interrupt for card status changes. This bit is encoded as:
0 = Host interrupt is edge-mode (default).
1 = Host interrupt is level-mode.
0
PWRDWN
RW
Power-down mode select. When this bit is set to 1, the PCI6515 controller is in power-down mode. In
power-down mode the PCI6515 card outputs are placed in a high-impedance state until an active cycle
is executed on the card interface. Following an active cycle the outputs are again placed in a
high-impedance state. The PCI6515 controller still receives functional interrupts and/or card status
change interrupts; however, an actual card access is required to wake up the interface. This bit is encoded
as:
0 = Power-down mode disabled (default)
1 = Power-down mode enabled
One or more bits in this register are cleared only by the assertion of GRST.
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