參數(shù)資料
型號(hào): PCI6515GHK
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述: 單插槽CardBus控制器,專用智能卡插槽
文件頁(yè)數(shù): 132/148頁(yè)
文件大小: 760K
代理商: PCI6515GHK
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78
7.12 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the Smart
Card interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt line
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
Interrupt line
3Ch
Read/Write
FFh
7.13 Interrupt Pin Register
This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 78, indicating
that the Smart Card interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits
are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.
If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the
PCI6515 controller asserts the USE_INTA input to the Smart Card controller core. If bit 28 (TIEALL) in the system
control register (PCI offset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted and
the interrupt for the Smart Card function is selected by the INT_SEL bits in the Smart Card general control register.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt pin
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
X
X
X
Register:
Offset:
Type:
Default:
Interrupt pin
3Dh
Read-only
0Xh
Table 78. PCI Interrupt Pin Register
INT_SEL BITS
USE_INTA
INTPIN
00
0
01h (INTA)
01
0
02h (INTB)
10
0
03h (INTC)
11
0
04h (INTD)
XX
1
01h (INTA)
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