參數(shù)資料
型號： PCI6515GHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 49/148頁
文件大?。?/td> 760K
代理商： PCI6515GHK
315
The
1997 PC Card Standard
describes the power-up sequence that must be followed by the PCI6515 controller when
an insertion event occurs and the host requests that the socket V
CC
and V
PP
be powered. Upon completion of this
power-up sequence, the PCI6515 interrupt scheme can be used to notify the host system (see Table 310), denoted
by the power cycle complete event. This interrupt source is considered a PCI6515 internal event, because it depends
on the completion of applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2
Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 310 by setting
the appropriate bits in the PCI6515 controller. By individually masking the interrupt sources listed, software can
control those events that cause a PCI6515 interrupt. Host software has some control over the system interrupt the
PCI6515 controller asserts by programming the appropriate routing registers. The PCI6515 controller allows host
software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing
somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections.
When an interrupt is signaled by the PCI6515 controller, the interrupt service routine must determine which of the
events listed in Table 39 caused the interrupt. Internal registers in the PCI6515 controller provide flags that report
the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be
taken.
Table 39 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the PCI6515 controller from passing PC Card functional interrupts through
to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there must
never be a card interrupt that does not require service after proper initialization.
Table 39 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing methods is made by
bit 2 (IFCMODE) in the ExCA global control register (ExCA offset 1Eh/81Eh, see Section 5.20), and defaults to the
flag-cleared-on-read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event
register (see Section 6.1). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software must not program the chip through both register sets when a CardBus card is functioning.
3.7.3
Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6MFUNC0, implemented in the PCI6515 controller can be routed to
obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use
the parallel ISA-type IRQ interrupt signaling, software must program the device control register (PCI offset 92h, see
Section 4.38), to select the parallel IRQ signaling scheme. See Section 4.35,
Multifunction Routing Status Register
,
for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket-services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. The INTRTIE bit is used, in this case, to route socket interrupt events to INTA. This leaves (at a
maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ9, IRQ10,
and IRQ15. The multifunction routing status register must be programmed to a value of 0A9F 5432h. This value
routes the MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 311. Not
shown is that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that
provides parallel PCI interrupts to the host.
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