參數(shù)資料
型號： PCI6515GHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 75/148頁
文件大小： 760K
代理商： PCI6515GHK
417
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. See Table 48 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
System control
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
R
R
R
R
Default
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
System control
Type
RW
RW
R
R
R
R
R
R
R
RW
RW
RW
RW
R
RW
RW
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
System control
80h (Function 0)
Read-only, Read/Write
0844 9060h
Table 48. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
3130
SER_STEP
RW
Serial input stepping. In serial PCI interrupt mode, these bits are used to configure the serial stream PCI
interrupt frames, and can be used to accomplish an even distribution of interrupts signaled on the four PCI
interrupt slots.
00 = INTA/INTB/INTC/INTD signal in INTA/INTB/INTC/INTD slots (default)
01 = INTA/INTB/INTC/INTD signal in INTB/INTC/INTD/INTA slots
10 = INTA/INTB/INTC/INTD signal in INTC/INTD/INTA/INTB slots
11 = INTA/INTB/INTC/INTD signal in INTD/INTA/INTB/INTC slots
29
INTRTIE
RW
This bit ties INTA to INTB internally (to INTA), and reports this through the interrupt pin register (PCI offset
3Dh, see Section 4.24). This bit has no effect on INTC or INTD.
28
TIEALL
RW
This bit ties INTA, INTB, INTC, and INTD internally (to INTA), and reports this through the interrupt pin
register (PCI offset 3Dh, see Section 4.24).
27
PSCCLK
RW
P2C power switch clock. The PCI6515 CLOCK signal clocks the serial interface power switch and the
internal state machine. The default state for this bit is 0, requiring an external clock source provided to the
CLOCK terminal. Bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal.
0 = CLOCK is provided externally, input to the PCI6515 controller.
1 = CLOCK is generated by the internal oscillator and driven by the PCI6515 controller. (default)
26
SMIROUTE
RW
SMI interrupt routing. This bit selects whether IRQ2 or CSC is signaled when a write occurs to power a
PC Card socket.
0 = PC Card power change interrupts are routed to IRQ2 (default).
1 = A CSC interrupt is generated on PC Card power changes.
25
SMISTATUS
RW
SMI interrupt status. This bit is set when a write occurs to set the socket power, and the SMIENB bit is set.
Writing a 1 to this bit clears the status.
0 = SMI interrupt is signaled.
1 = SMI interrupt is not signaled.
24
SMIENB
RW
SMI interrupt mode enable. When this bit is set, the SMI interrupt signaling generates an interrupt when
a write to the socket power control occurs. This bit defaults to 0 (disabled).
0 = SMI interrupt mode is disabled (default).
1 = SMI interrupt mode is enabled.
23
RSVD
R
Reserved
One or more bits in this register are cleared only by the assertion of GRST.
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