參數(shù)資料
型號(hào)： PC28F256J3C-150
廠商： Intel Corp.
英文描述： Intel StrataFlash Memory (J3)
中文描述： 英特爾StrataFlash存儲(chǔ)器（J3）
文件頁(yè)數(shù)： 9/72頁(yè)
文件大小： 905K
代理商： PC28F256J3C-150
256-Mbit J3 (x8/x16)
Datasheet
9
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS signal to be configured to
pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (see
Table 13, “Chip Enable Truth Table” on page 33
) reduces decoder logic typically required for
multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-
chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 4 on page 14.
When the device is disabled (see
Table 13 on page 33
), with CEx at V
IH
and RP# at V
IH
, the
standby mode is enabled. When RP# is at V
IL
, a further power-down mode is enabled which
minimizes power consumption and provides write protection during reset. A reset time (t
PHQV
) is
required from RP# going high until data outputs are valid. Likewise, the device has a wake time
(t
PHWL
) from RP#-high until writes to the CUI are recognized. With RP# at V
IL
, the WSM is reset
and the Status Register is cleared.
2.1
Block Diagram
Figure 1. 3 Volt Intel StrataFlash
Memory Block Diagram
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
128-Kbyte Blocks
Input Buffer
O
L
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
D
R
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output
Buffer
GND
VCC
BYTE#
VPEN
CE0
CE1
CE2
WE#
OE#
RP#
Command
User
Interface
A[MAX:MIN]
D[15:0]
VCC
W
Write State
Machine
Multiplexer
Query
STS
VCCQ
CE
Logic
A[2:0]
相關(guān)PDF資料
PDF描述
PC28F128J3A-110 Intel StrataFlash Memory (J3)
PC28F128J3A-115 Intel StrataFlash Memory (J3)
PC28F640J3C-125 Intel StrataFlash Memory (J3)
PC28F640J3C-150 Intel StrataFlash Memory (J3)
PC28F640J3A-110 Intel StrataFlash Memory (J3)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PC28F256J3D95A 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ
PC28F256J3D95B 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ
PC28F256J3F950 制造商:Micron Technology Inc 功能描述:256MB, TURLOCK EBGA 3.0 LF - Trays
PC28F256J3F95A 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR)
PC28F256J3F95B 制造商:Micron Technology Inc 功能描述:16MX16 NOR FLASH PLASTIC PBF TBGA 3.0V - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*