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參數(shù)資料
| 型號： | PC28F256J3C-150 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 47/72頁 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-150 |
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256-Mbit J3 (x8/x16)
Datasheet
47
This two-step sequence of setup followed by execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and
SR.5 being set. Also, a reliable clear block lock-bits operation can only occur when V
CC
and V
PEN
are valid. If a clear block lock-bits operation is attempted while V
PEN
≤
V
PENLK
, SR.3 and SR.5
will be set.
If a clear block lock-bits operation is aborted due to V
PEN
or V
CC
transitioning out of valid range,
block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required
to initialize block lock-bit contents to known values.
13.3
Protection Register Program
The Intel StrataFlash
memory (J3) includes a 128-bit Protection Register (PR) that can be used to
increase the security of a system design. For example, the number contained in the PR can be used
to “mate” the flash component with other system components such as the CPU or ASIC, preventing
device substitution.
The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at
the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank
for customer designers to program as desired. Once the customer segment is programmed, it can be
locked to prevent further programming.
13.3.1
Reading the Protection Register
The Protection Register is read in the identification read mode. The device is switched to this mode
by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses
shown in
Table 8
or
Table 21
retrieve the specified information. To return to read array mode, write
the Read Array command (0xFF).
13.3.2
Programming the Protection Register
Protection Register bits are programmed using the two-cycle Protection Program command. The
64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time
for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next
write to the device will latch in address and data and program the specified location. The allowable
addresses are shown in
Table 8
or
Table 21
. See
Figure 26, “Protection Register Programming
Flowchart” on page 67
Any attempt to address Protection Program commands outside the defined PR address space will
result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will
result in a Status Register error (SR.4 and SR.1 will be set).
13.3.3
Locking the Protection Register
The user-programmable segment of the Protection Register is lockable by programming Bit 1 of
the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique
device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the
PLR. After these bits have been programmed, no further changes can be made to the values stored
in the Protection Register. Protection Program commands to a locked section will result in a Status
Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.
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| PC28F256J3D95A | 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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