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參數(shù)資料
| 型號： | PC28F256J3C-110 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 69/72頁 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-110 |
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256-Mbit J3 (x8/x16)
Datasheet
69
C.4
V
CC
, V
PEN
, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if V
PEN
or V
CC
falls outside of
the specified operating ranges, or RP#
≠
V
IH
. If RP# transitions to V
IL
during block erase,
program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of
t
PLPH
+ t
PHRH
until the reset operation is complete. Then, the operation will abort and the device
will enter reset/power-down mode. The aborted operation may leave data partially corrupted after
programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase
and lock-bit configuration commands must be repeated after normal operation is restored. Device
power-off or RP# = V
IL
clears the Status Register.
The CUI latches commands issued by system software and is not altered by V
PEN
, CE
0
, CE
1
, or
CE
2
transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/
power-down mode, or after V
CC
transitions below V
LKO
. V
CC
must be kept at or above V
PEN
during V
CC
transitions.
After block erase, program, or lock-bit configuration, even after V
PEN
transitions down to V
PENLK
,
the CUI must be placed in read array mode via the Read Array command if subsequent access to
the memory array is desired. V
PEN
must be kept at or below V
CC
during V
PEN
transitions.
C.5
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s
nonvolatility increases usable battery life because data is retained when system power is removed.
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