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參數(shù)資料
| 型號： | PA28F002BC-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 80 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 33/37頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PA28F002BC-T80 |
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E
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
33
PRELIMINARY
Table 10. AC Characteristics: CE#
—Controlled Write Operations
(1,9)
28F002BC-80
28F002BC-120
Symbol
Parameter
Notes
V
CC
= 5V ± 10%
100 pF
V
CC
= 5V ± 10%
100 pF
Units
Min
Max
Min
Max
t
AVAV
Write Cycle Time
80
120
ns
t
PHEL
RP# High Recovery to CE# Going
Low
215
215
ns
t
WLEL
WE# Setup to CE# Going Low
0
0
ns
t
PHHEH
Boot Block Lock Setup to CE# Going
High
V
PP
Setup to CE# Going High
6, 8
100
100
ns
t
VPEH
5, 8
100
100
ns
t
AVEH
Address Setup to CE# Going High
3
50
50
ns
t
DVEH
Data Setup to CE# Going High
4
50
50
ns
t
ELEH
CE# Pulse Width
50
50
ns
t
EHDX
Data Hold Time from CE# High
4
0
0
ns
t
EHAX
Address Hold Time from CE# High
3
0
0
ns
t
EHWH
WE # Hold Time from CE# High
0
0
ns
t
EHEL
CE# Pulse Width High
30
30
ns
t
EHQV1
Duration of Programming Operation
2, 5
6
6
μs
t
EHQV2
Duration of Erase Operation (Boot)
2, 5, 6
0.3
0.3
s
t
EHQV3
Duration of Erase Operation
(Parameter)
2, 5
0.3
0.3
s
t
EHQV4
Duration of Erase Operation (Main)
2, 5
0.6
0.6
s
t
QVVL
V
PP
Hold from Valid SRD
5, 8
0
0
ns
t
QVPH
RP# V
HH
Hold from Valid SRD
6, 8
0
0
ns
t
PHBR
Boot Block Lock Delay
7, 8
100
100
ns
NOTES:
See WE# Controlled Write Operations for notes 1 through 8.
9.
Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
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