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參數(shù)資料
| 型號： | PA28F002BC-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 80 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 23/37頁 |
| 文件大?。?/td> | 455K |
| 代理商： | PA28F002BC-T80 |
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E
3.5
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
23
PRELIMINARY
Power Consumption
3.5.1
ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the device is placed in the active mode.
The device I
CC
current is a maximum of 60 mA at
10 MHz with TTL input signals.
3.5.2
STANDBY POWER
With CE# at a logic-high level (V
IH
), the memory is
placed in standby mode, where the maximum I
CC
standby current is 100
μ
A. The standby operation
disables much of the device’s circuitry and
substantially reduces device power consumption.
The outputs (DQ[0:7]) are placed in a high-
impedance state independent of the status of the
OE# signal. When CE# is at a logic-high level
during erase or program, the device will continue to
perform the erase or program function and
consume erase or program active power until erase
or program is completed.
3.5.3
DEEP POWER-DOWN
The 28F002BC flash memory supports a typical I
CC
of 0.2
μ
A in deep power-down mode. This mode is
activated by the RP# pin when it is at a logic-low
(GND
±
0.2V); in this mode, all internal circuits are
turned off to save power.
Setting the RP# pin low de-selects the memory and
places the output drivers in a high impedance state.
Recovery from the deep power-down state requires
a minimum access time of 300 ns (see AC
Characteristics table, t
PHQV
parameter).
During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as the data has been
corrupted. RP# transitions to V
or turning power
off to the device will clear the status register.
3.6
Power-Up/Down Operation
The 28F002BC offers protection against accidental
block erasure or programming during power
transitions.
Power supply sequencing is not
required
, since
the device is indifferent as to which
power supply, V
PP
or V
CC
, powers-up first. The CUI
is reset to the read mode after power-up, but the
system must drop CE# low or present a new
address to ensure valid data at the outputs.
A system designer must guard against spurious
writes when V
CC
voltages are above V
LKO
and V
PP
= V
HH
. Since both WE# and CE# must be low for a
command write, driving either signal to V
IH
will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
V
IH
, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to
system PowerGood/Reset) during power up/down,
invalid bus conditions during power-up can be
masked, providing yet another level of memory
protection.
3.6.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated write/erase devices because the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.
3.6.2
V
CC
, V
PP
AND RP# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
, CE# transitions,
or WSM actions. Its default state upon power-up,
after exit from deep power-down mode, or after V
CC
transitions above V
LKO
, is read array mode.
After any program or block erase operation is
complete, and even after V
PP
transitions down to
V
PPLK
, the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory is desired.
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