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參數(shù)資料
| 型號： | P95020ZNQGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | QFN-132 |
| 文件頁數(shù)： | 37/137頁 |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZNQGI |
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P95020 / Preliminary Datasheet
Revision 0.7.10
131
2010 Integrated Device Technology, Inc.
17.0 EMBUP
– EMBEDDED MICROCONTROLLER SUBSYSTEM & I/O
FEATURES
Power Up/Down Sequencing
Eliminates the need for the AP or another external
controller (PLD/PIC) to perform this function.
Improves system power consumption by offloading this task
from the higher power application processor.
General monitoring and action based on external or
internal events such as:
ADC Result
Power Supply Fault Monitoring
Other System Interrupts
DESCRIPTION
The Embedded Microcontroller (EMBUP) of the P95020
can operate in one of two modes: mixed mode or stand-
alone
mode.
In
mixed
mode,
both
the
internal
microcontroller and an external Application Processor
(AP) can also control some or all of the P95020
subsystems.
In
stand-alone
mode,
the
EMBUP
completely offloads power sequencing and other functions
from the application processor so that the processor can
perform other functions or spend more time in sleep
mode.
The microcontroller core runs at 8 MHz with a 1.8V power
supply and can be shut off if required.
It interfaces
through VSYS level signals (3.0 to 5.5V) and supports the
following functions:
Device initialization
Power sequencing for power state transitioning
Keyboard scanning
Enable/Disable of all Interfaces and Sub-Modules
17.1
OVERVIEW
Module
Interrupts
Usage
ACCM
Message signaling
1
Internal /external processor communication
CHGR
Adapter In/ Charging state change
3
Charger state detection
CLASSD-Driver
Fault
1
DCDC
Fault
1
GPTIMER
General purpose timer, Watchdog timer
2
LDO
Fault
1
GPIO
GPIO/SW_DET
10/2
System power on/off
RTC
Alarm-1, Alarm-2
2
TSC
Pendown
1
TSC
Die temperature high,
Battery voltage low,
VSYS voltage low
3
17.2 FUNCTIONAL DESCRIPTION
After a Power on Reset (POR), the P95020 embedded microcontroller will look for the presence of an external ROM via
the EX_ROM pin. If an external ROM is present, the P95020 embedded microcontroller will disable the internal ROM,
and load the contents into a 1.5 KB internal RAM from which it can be executed. If no external ROM is present, then the
internal ROM will be used for program code.
The P95020 embedded microcontroller will execute the start-up sequence contained in the internal or external ROM and
will set the various registers accordingly (all internal registers are available for manipulation by an external application
processor through the IC interface at all times). Once the registers have been programmed, the embedded
microcontroller will either run additional program code or go into standby until an interrupt or other activity generates a
wake event. Various events will be customer specific but could include power saving modes, sleep modes, over-
temperature conditions, etc.
Contention caused by requests from both the embedded microcontroller and external processor is resolved through a bus
arbitration scheme. There is no support for data concurrency in the register set. The P95020 will execute the latest (last)
data/command programmed into any individual control register(s) regardless of the source (embedded microcontroller or
external application processor). Care should be taken during the code development stage to avoid command contention.
17.3 ON-CHIP RAM & ROM
Memory Type
Size
ROM
4 k Bytes Maximum
RAM
1.5 k Bytes Maximum
17.4 IC SLAVE INTERFACE
Please see the separate I2C_I2S Module in Section 15.0 for details (including register definitions).
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