參數(shù)資料
型號： P95020ZNQGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數(shù)： 24/137頁
文件大?。?/td> 3533K
代理商： P95020ZNQGI
P95020 / Preliminary Datasheet
Revision 0.7.10
12
2010 Integrated Device Technology, Inc.
MODULE
PIN #
PIN NAME
DESCRIPTION
I/O TYPE
B6
MIC_L-
MIC_L- : Analog Microphone Differential Stereo Left Inverting Input
A-I
A8
AFILT2
Microphone ADC Anti-Aliasing Filter Capacitor #2
A-I
B7
AFILT1
Microphone ADC Anti-Aliasing Filter Capacitor #1
A-I
A9
AGND_MIC
Microphone Ground (Analog Ground)
GND
B8
LISLP
Line Input Stereo Left Non-Inverting
A-I
A10
LISLM
Line Input Stereo Left Inverting
A-I
B9
LISRP
Line Input Stereo Right Non-Inverting
A-I
A11
LISRM
Line Input Stereo Right Inverting
A-I
B10
LLO_L
Line Level Output, Left
A-O
A12
AVREF
Analog Reference
A-O
B11
LLO_R
Line Level Output, Right
A-O
A13
ADC_REF
ADC Reference Bypass Capacitor
A-I
B12
VDD_AUDIO33
Filter Capacitor for Internal 3.3V AUDIO LDO
A-O
A14
HP_L
Left Headphone Output
A-O
B13
HP_R
Right Headphone Output
A-O
A15
VIRT_GND
Virtual Ground for Cap-Less Output
A-O
B14
AGND
Analog Ground
GND
LDO
A16
LDO_IN3
Input Voltage to LDOs for AUDIO Power
(VDD_AUDIO33 & VDD_AUDIO18)
AP-I
B15
LDO_GND
LDO Ground
GND
A17
NC
No Connect
NC
A18
LDO_LP
Always on Low Power LDO Output
(Voltage Programmable to 3.0 V or 3.3 V)
AP-O
A19
LDO_050_3
50mA LDO Output #3 (Voltage Range: 0.75-3.7 V)
AP-O
A20
NC
No Connect
NC
B16
LDO_050_2
50mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
AP-O
A21
LDO_IN2
Input Voltage to LDO_050_0, LDO_050_1, LDO_050_2 & LDO_050_3
AP-I
B17
LDO_050_1
50mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
AP-O
A22
LDO_050_0
50mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
Note: This LDO also serves as the internal power source for I2S1, I2S2 and
I2CS. The external function of this pin is not affected but the voltage
register setting for this LDO will also govern the I/O level for I2S1, I2S2 and
I2CS.
AP-O
B18
LDO_150_2
150mA LDO Output #2 (Voltage Range: 0.75-3.7 V)
AP-O
A23
LDO_IN1
Input Voltage to LDO_150_0, LDO_150_1 & LDO_150_2
AP-I
B19
LDO_150_1
150mA LDO Output #1 (Voltage Range: 0.75-3.7 V)
AP-O
A24
LDO_150_0
150mA LDO Output #0 (Voltage Range: 0.75-3.7 V)
AP-O
CK_GEN
B20
32KHZ_OUT2
Buffered 32.768kHz Output #2
D-O
A25
CKGEN_GND
PLL Analog Ground
GND
B21
32KHZ_CLKIN/XTALIN
32KHZ_CLKIN: External 32.768kHz Clock Input;
A-I
XTALIN : Input Pin when used with an external crystal
A26
XTALOUT/32KHZ_OUT1
XTALOUT: Output Pin when used with an external crystal
A-O
32KHZ_OUT1: when XTALIN is connected to a 32kHz input this pin can be
a 32kHz Output when CKGEN_PLL_STATUS register, 32KOUT1_EN (bit
4) is set to 1.
B22
VDD_CKGEN18
Filter Capacitor for Internal 1.8V CKGEN LDO
A-IO
A27
HXTALOUT/TCXO_IN
HXTALOUT: 12 MHz, 13 MHz, 19.2 MHz or 26 MHz output
TCXO-D-I
TCXO_IN: External 12 MHz, 13 MHz, 19.2 MHz or 26 MHz clock input
B23
VDD_CKGEN33
Filter Capacitor for Internal 3.3V CKGEN LDO
A-IO
A28
HXTALIN/TCXO_OUT1
HXTALIN: 12 MHz, 13 MHz, 19.2 MHz, or 26 MHz crystal oscillator input
TCXO-D-O
TCXO_OUT1: Buffered HXTALOUT/TCXO_IN Clock Output #1, 32.7638
KHz Output or 24 MHz PLL Output
B24
TCXO_OUT2
Buffered HXTALOUT/TXCO_IN Clock Output #2, 12 MHz PLL Output or 48
MHz PLL Output
TCXO-D-O
A29
SYS_CLK
12MHz Output or Buffered Output of TCXO_IN
D-O
B25
CKGEN_GND
PLL Analog Ground
GND
A30
USB_CLK
24 MHz or 48 MHz Output
D-O
B26
VDDIO_CK
Power Supply Input for TCXO_OUT1 and TCXO_OUT2 (1.1V
– 1.9V)
AP-I
I2C_I2S
A31
EX_ROM
ROM Select. EX_ROM = 1, read contents of external ROM. EX_ROM = 0,
read contents of internal ROM into internal shadow memory.
D-I
B27
DGND
Digital Ground (1)
GND
A32
I2S_BCLK2
IS Bit Clock Channel 2
D-I
B28
I2S_WS2
IS Word Select (Left/Right) Channel 2
D-I
A33
I2S_SDIN2
IS Serial Data IN Channel 2
D-I
B29
I2S_SDOUT2
IS Serial Data OUT Channel 2
D-O
A34
I2S_WS1
IS Word Select (Left/Right) Channel 1
D-I
B30
I2S_BCLK1
IS Bit Clock Channel 1
D-I
A35
NC
No Connect
NC
A36
NC
No Connect
NC
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