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參數(shù)資料
| 型號(hào)： | P95020ZNQGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | QFN-132 |
| 文件頁(yè)數(shù)： | 11/137頁(yè) |
| 文件大小： | 3533K |
| 代理商： | P95020ZNQGI |
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P95020 / Preliminary Datasheet
Revision 0.7.10
108
2010 Integrated Device Technology, Inc.
The firmware (boot sequence) starts with checking whether the external ROM is available (read EX_ROM bit in
the global registers). If it exists, load the EX_ROM data into internal RAM. Other wise, execute code in the
internal ROM.
Firmware execute the code according the context and interrupt to sequence the power.
After the sequence is done, processor enter low power mode and wait for interrupts.
13.4 POWER ON RESET OUTPUT (POR_OUT)
The POR_OUT pin is an open drain GPIO output pin which controlled by firmware as part of the power up sequence. This
signal is used to reset the devices in the system that are powered by P95020 device while the power is not yet ready. The
output state of POR_OUT is defined by the power up sequence.
13.5 POWER SWITCH DETECTOR (SW_DET)
The PCON module also includes special power switch detection
circuitry to provide a “push-on/push-off” interface via the
switch detect (SW_DET) pin. By connecting a button to this pin, three different events can be triggered. The first is a
short switch interrupt (>100ms) which is generated by momentarily pressing and releasing a button attached to SW_DET.
The second is a medium switch interrupt which is generated by pressing and holding the button and releasing it after 2
seconds (configurable to 2/3/4/5 seconds). The status of each of these switches can be monitored in the Switch Control
Register (0xA031). The third switch function is triggered when the button is pressed and held for longer than 15 seconds.
This event will not generate an interrupt but will generate system reset and force P95020 into OFF state.
13.6 GPIO GENERAL DESCRIPTION
The GPIO pins are turned on and off using the GPIO Off Register. This register is used like a multiplexer to allow the
GPIO and TSC/ADC subsystems to share external pins. W
hen in GPIO mode (GPIO_OFF bits set to logic 0) the GPIO
Function Register configures the pin to operate as a GPIO or some other special function such as a status LED output. If
not configured to perform a special function, each GPIO can be configured as an input or output by setting the
corresponding bit in the GPIO Direction Register.
When configured as an output, each GPIO pin can be configured as a CMOS output or an open drain output by setting
the corresponding bit in the GPIO Output Mode Register. Each GPIO pin configured as an output will reflect the value
held in the GPIO Data Register with a logic 0 causing the pin to be low and a logic 1 causing the pin to be high.
Reading from the GPIO Data Register will return the last value written to it.
When configured as an input, each GPIO can be configured as level or edge sensitive by setting the corresponding bit in
the GPIO Input Mode Select Register. When set to level sensitive, the corresponding bit in the GPIO Data Register will
follow the logic level of the GPIO pin. When set to edge sensitive the corresponding bit in the GPIO Data Register will
change from a logic 0 to a logic 1 when the input transitions from low to high (rising edge) or high to low (falling edge) as
determined by the setting in the GPIO Input Edge Select Register. The value in the GPIO Data Register will remain a
logic 1 until a logic 0 is written into the register throuigh host or I2C interface. In level sensitive mode, writing to the
GPIO Data Register through host or I2C will have no effect.
When configured as an input, a GPIO may also generate an interrupt. Interrupts are always edge sensitive. The GPIO
Input Edge Select Register is used to select which edge, rising or falling, is used to generate an interrupt. When as edge
is detected, the GPIO Interrupt Status Register will show a logic 1 in the corresponding bit and an interrupt will be
generated provided the appropriate bit has been enabled by writing a
logic 1 to the GPIO Interrupt Enable Register. The
GPIO Interrupt Status Register is cleared by writing a logic 1 to the appropriate bit. Writing a logic 0 will have no effect.
13.7 PCON REGISTERS
13.7.1
GPIO DIRECTION REGISTER
IC Address = Page-0: 32(0x20), C Address = 0xA020
IC Address = Page-0: 33(0x21), C Address = 0xA021
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
RESERVED
0b
R/W
RESERVED
[10:1]
GPIO_DIR
0000000000b
R/W
0 = Input
1 = Output
Each bit sets the corresponding GPIO to either input or output
[15:11]
RESERVED
R/W
RESERVED
13.7.2
GPIO DATA REGISTER
IC Address = Page-0: 34(0x22), C Address = 0xA022
IC Address = Page-0: 35(0x23), C Address = 0xA023
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