參數資料
型號： P95020ZNQGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數： 106/137頁
文件大?。?/td> 3533K
代理商： P95020ZNQGI
P95020 / Preliminary Datasheet
Revision 0.7.10
70
2010 Integrated Device Technology, Inc.
5.5.1
RTC_INT_CTL
– RTC Interrupt Control Register
IC Address = Page-0: 79(0x4F), C Address = 0xA04F
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
A1_EN
0b
R/W
1: interrupt enable
0: interrupt disable
Alarm 1 interrupt enable
1
A2_EN
0b
R/W
1: interrupt enable
0: interrupt disable
Alarm 2 interrupt enable
[7:2]
RESERVED
R/W
RESERVED
5.5.2
RTC_INT_ST
– RTC Interrupt Status Register
A logic 1 in the A1_FLAG bit indicates that the time matched the value programmed into the registers for alarm 1. If the
A1_EN bit is set to a logic 1 at the time the A1_FLAG goes to logic 1, the INT pin will be asserted. The A1_FLAG is
cleared when a logic 1 is written to this register location. This bit can only be written to logic 1. Attempting to write a
logic 0 leaves the value unchanged.
A logic 1 in the A2_FLAG bit indicates that the time matched the value programmed into the registers for alarm 2. If the
A2_EN bit is set to a logic 1 at the time the A2_FLAG goes to logic 1, the INT pin will be asserted. The A2_FLAG is
cleared when a logic 1 is written to this register location. This bit can only be written to logic 1. Attempting to write a
logic 0 leaves the value unchanged.
IC Address = Page-0: 80(0x50), C Address = 0xA050
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
A1_FLAG
0b
RW1C
1: time match alarm 1 value
0: No match
Alarm 1 interrupt flag
1
A2_FLAG
0b
RW1C
1: time match alarm 2 value
0: No match
Alarm 2 interrupt flag
[7:2]
RESERVED
R/W
RESERVED
5.6
RTC RESERVED REGISTERS
5.6.1
RTC - RESERVED Registers
These registers are reserved. Do not write to them.
IC Address = Page-0: 81(0x51), C Address = 0xA051
IC Address = Page-0: 94(0x5F), C Address = 0xA05F
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