參數(shù)資料
型號： P95020ZNQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數(shù)： 68/137頁
文件大?。?/td> 3533K
代理商： P95020ZNQG
P95020 / Preliminary Datasheet
Revision 0.7.10
36
2010 Integrated Device Technology, Inc.
2.13.10 AUDIO CLASS_D - GAINCTRL Registers
This is a 16-bit register = {GAINCTRL_HI, GAINCTRL_LO}.
GAINCTRL_HI: IC Address = Page-2: 35(0x23), C Address = 0xA223
GAINCTRL_LO: IC Address = Page-2: 36(0x24), C Address = 0xA224
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
0
mute_mode
1b
RW
0 = soft mute
1 = hard mute
Mute After Reset
1
change_mode
0b
RW
0 = change on zero
cross
1 = change gain
immediately
Gain Change Mode
2
auto_mute
1b
RW
0 = Dont Auto Mute
1 = Auto Mute
Auto Mute if long string of zeros detected on input
3
disable_gain
0b
RW
0 = Dont Disable
1 = Disable
Disable All Gain Functions (Bypass Gain Multiply)
4
stepped_change
0b
RW
0 = Dont Step
1 = Step
Step Volume Progressively to New Setting
5
step_10ms
0b
RW
0 = 1 ms
1 = 10 ms
Units for step_time Value
6
RESERVED
0b
RW
RESERVED
7
clr_latch
0b
RW
0 = Dont Clear
1 = Clear Limit
1 = clear limit 0/1 latches, see STATUS2 reg
[10:8]
step_time
101b
RW
0 =
1 units
1 =
2 units
2 =
4 units
3 =
8 units
4 = 16 units
5 = 32 units
6 = 64 units
7 = 128 units
Step time units = 1 << step_time
Unit range is defined in GAINCTRL_LO, bit 5
[12:11]
zerodetlen
10b
RW
0 = 512 Samples
1 = 1k Samples
2 = 2k Samples
3 = 4k Samples
Enable mute if input consecutive zeros exceeds this length.
[15:13]
RESERVED
000b
RW
RESERVED
2.13.11 AUDIO CLASS_D - MUTE Register
Enable mute individually per channel via this register. Global mute is available via CONFIG0[1].
MUTE: IC Address = Page-2: 38(0x26), C Address = 0xA226
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
0
mute0
0b
RW
0 = Dont Mute
1 = Mute
Mute Channel 0
1
mute1
0b
RW
0 = Dont Mute
1 = Mute
Mute Channel 1
[7:2]
RESERVED
000000b
RW
RESERVED
2.13.12 AUDIO CLASS_D
– ATTEN Register
This is the master attenuation which is applied to all channels.
ATTEN: IC Address = Page-2: 39(0x27), C Address = 0xA227
Bit
Bit Name
Default
Settings
User
Type
Value
Description / Comments
[7:0]
ATTEN
00h
RW
00h =
0 dB
01h = -0.5 dB
02h = -1.0 db
...
47h = -35.5 dB
48h = -36.0 dB
49h = -36.5 dB
...
FEh = -127 dB
FFh = Hard Master
Mute
Attenuation. Each bit represents 0.5 dB of attenuation to be applied
to the channel. The range will be from 127 dB to 0 dB.
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