參數(shù)資料
型號(hào)： P95020ZNQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁(yè)數(shù)： 51/137頁(yè)
文件大小： 3533K
代理商： P95020ZNQG
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P95020 / Preliminary Datasheet
Revision 0.7.10
20
2010 Integrated Device Technology, Inc.
1.2
REGISTER MAP
All the P95020 control and status registers accessible to the Microprocessor are mapped to a 1024 location address
space. This address space maps to:
4 x 256 Bytes of IC pages for the IC slave interface
1024 consecutive addresses in the embedded Microprocessor address space
For easy access from the IC slave interface (by default 256 Bytes oriented) the first 16 registers of each page are global
for all the pages.
Each Module is allocated a consecutive address space.
Register address computation: Address = Base Address + Offset Address
The Base addresses (for both IC and embedded uP) are listed in the following table. The Offset addresses are defined in
different functional Modules. The offset address is labeled as
“Offset Address” in the Module Register definition sections.
Table 3 – Register Address Global Mapping
Module
Size
(Bytes)
Base Address
(IC)
Base Address
(6811
P)
Register Definition
Location
Module Description
Global Registers
16
Page-x:
000(0x00)
0xA000
Page 120 Section 15.7
Global registers are used by the Access
Manager, the first 16 registers of each page
are global for all the pages.
ACCM
16
Page-0:
016(0x10)
0xA010
Page 123 Section 15.8
Access manager, including an IC slave and
bus arbiter
PCON
32
Page-0:
032(0x20)
0xA020
Page 108 Section 13.7.1
Power controller, including registers that
control the on/off of the regulators, and
control/sense of the GPIO, power states
Page 64 Section 4.7
Clock Generator Registers
RTC
32
Page-0:
064(0x40)
0xA040
Page 67 Section 5.2
Real Time Clock
LDO
32
Page-0:
096(0x60)
0xA060
Page 127 Section 16.6
Linear regulators, including regulators for
external and internal usage
DC_DC
16
Page-0:
128(0x80)
0xA080
Page 74 Section 7.0
Switching regulators and Class-D BTL driver
consisting of three bucks, one 5V boost , one
white LED driver and one Class-D BTL driver
CHARGER
16
Page-0:
144(0x90)
0xA090
Page 55 Section 3.5
Battery Charger, including a dedicated
switching buck regulator, an ideal diode, a
precision reference and thermal sensor
GPT
16
Page-0:
160(0xA0)
0xA0A0
Page 71 Section 6.2
General purpose timers
RESERVED
16
Page-0:
176(0xB0)
0xA0B0
RESERVED
ADC_TSC
64
Page-0:
192(0xC0)
0xA0C0
Page 100 Section 12.4
Touch-screen (ADC, pendown detect and
switches, temperature and battery voltage
monitoring), and GPIOs
AUDIO
240
Page-1:
000(0x00)
0xA100
Page 40 Section 2.15
Audio subsystem, excluding class-D amplifier
CLASS_D_DIG
240
Page-2:
000(0x00)
0xA200
Page 32 Section 2.13
Class-D amplifier digital processing part
RESERVED
240
Page-3:
000(0x00)
0xA300
RESERVED
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