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參數(shù)資料
| 型號(hào)： | P95020ZNQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | QFN-132 |
| 文件頁(yè)數(shù)： | 107/137頁(yè) |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZNQG |
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P95020 / Preliminary Datasheet
Revision 0.7.10
71
2010 Integrated Device Technology, Inc.
6.0 GENERAL PURPOSE TIMERS
6.1
GENERAL PURPOSE TIMERS
– GENERAL DESCRIPTION
The P95020 includes two independent general purpose timers. The first is an 8-bit General Purpose Timer that operates
on a user-selectable time base of 32.768 kHz, 1024 Hz, 1Hz, or 1 Minute. The second is an 8-bit Watchdog Timer that
operates on a user-selectable time base of 8Hz, 1Hz, 0.5Hz, or 1 Minute
6.1.1
GENERAL PURPOSE TIMER
To use the General Purpose Timer (GP), an 8-bit value must be loaded in to the General Purpose Timer Count Register
and a time base (count interval) value must also be loaded into bits [1:0] of the General Purpose Timer Timebase
Register. The General Purpose Timer can then be enabled by wr
iting a logic 1 into bit 0 (GPT_EN) of the General
Purpose Timer Enable Register. The General Purpose Timer will then begin counting and continue until the count value
is equal to the value specified in the General Purpose Timer Count Register (timeout value). When the timeout value is
reached, the GPTIMEOUT bit is set to a logic 1 in the Timer Interrupt Status Register. If the General Purpose Timer
Interrupt
has been enabled by setting bit 0 in the Timer Interupt Register to a logic 1 then an interrupt is generated to
alert the system that the timeout value has been reached. THE GPTIMEOUT bit is cleared by writing a logic 1 to the
GPTIMEOUT bit in the Timer Interrupt Status Register. Following the interrupt, the General Purpose Timer will stop and
reset to 0. Bit 0 of the General Purpose Timer Enable Register is also reset to 0 following the interrupt. However, the
content of General Purpose Timer Count Register and the General Purpose Timer Timebase Value Registers are
maintained and the co
unt cycle can be repeated by writing a logic 1 to GPT_EN. When the General Purpose Timer is
counting, writing a logic 0 to GPT_EN will reset and stop the timer.
6.1.2
WATCHDOG TIMER
To use the Watchdog Timer (WD), an 8-bit value must be loaded in to the Watchdog Timer Count Register and a time
base (count interval) value must also be loaded into bits [5:4] of the General Purpose Timer Timebase Register. The
Watchdog Timer can then be enabled by writing a logic 1 into bit 0 (WDT_EN) of the Watchdog Timer Enable Register.
The Watchdog Timer will then begin counting and continue until the count value is equal to the value specified in the
Watchdog Timer Count Register (timeout value). When the timeout value is reached, the WDTIMEOUT bit is set to a
logic
1 in the Timer Interrupt Status Register. If the Watchdog Timer Interrupt has been enabled by setting bit 4 in the
Timer Interrupt Register to a logic 1 then an interrupt is generated to alert the system that the timeout value has been
reached. THE
WDTIMEOUT bit is cleared by writing a logic 1 to the WDTIMEOUT bit in the Timer Interrupt Status
Register. Following the interrupt, the Watchdog Timer will stop and reset to 0. Bit 0 of the Watchdog Timer Enable
Register is also reset to 0 following the interrupt. The Watchdog Timer can be reset anytime during the count interval by
writing a logic 1 to bit 4 of the Watchdog Timer Enable Register before the timer times out to prevent an interrupt from
being generated. After reset the Watchdog Timer restarts automatically.
6.2
GENERAL PURPOSE TIMERS
– REGISTERS
6.2.1
PCON_GPT - GENERAL PURPOSE TIMER GLOBAL ENABLE REGISTER
IC Address = Page-0: 58(0x3A), C Address = 0xA03A
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
GPT_G_EN
0b
R/W
0 = Disabled
1 = Enabled
Enable GPT. Disabled GPT retains time value settings but the clock
is gated (low power mode).
[7:1]
RESERVED
R/W
RESERVED
6.2.2
WATCHDOG TIMER ENABLE REGISTER
IC Address = Page-0: 160(0xA0), C Address = 0xA0A0
Bit
Bit Name
Def.
Set.
User
Type
Value
Description / Comments
0
WDT_EN
0b
R/W
0 = Reset
1 = enable count
Watchdog timer enable/disable
[3:1]
RESERVED
R/W
RESERVED
4
WDT_RST
0b
R/W1A
Write 1 to reset. Read
always returns 0.
Watchdog timer reset. Write 1 to reset. Read always returns 0.
[7:5]
RESERVED
R/W
RESERVED
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