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參數(shù)資料
| 型號： | P95020ZNQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | QFN-132 |
| 文件頁數(shù)： | 10/137頁 |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZNQG |
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P95020 / Preliminary Datasheet
Revision 0.7.10
107
2010 Integrated Device Technology, Inc.
13.0 PCON MODULE
– POWER CONTROLLER AND GENERAL PURPOSE I/O
PCON Module is the power controller of the device. It also manages the registers associated with GPIO and CKGEN.
13.1
13.1 GPIO PIN DEFINITIONS
PIN #
PIN_ID
DESCRIPTION
117
GND_BAT/ADCGND
GND_BAT & ADCGND: Shared analog ground pin for battery charger and ADC
118
DGND
Digital Ground
119
POR_OUT
Power-On Reset Output, Open-drain Output, Active Low
120
SW_DET
Switch Detect Input
121
GPIO1 / SW_OUT / PENDOWN
GPIO 1: General Purpose I/O # 1
SW_OUT: Switch Detect Output
PENDOWN: Pen down
122
GPIO2 / LED1
GPIO 2: General Purpose I/O # 2
LED1: Charger LED # 1 Indicates charging in progress
123
GPIO3 / LED2
GPIO 3: General Purpose I/O # 3
LED2: Charger LED # 2 Indicates charging complete
124
GPIO4 / CHRG_ILIM
GPIO 4: General Purpose I/O # 4
CHRG_ILIM
001
GPIO5 / INT_OUT
GPIO 5: General Purpose I/O # 5
INT_OUT : Interrupt Output
002
GPIO6 / ADC1
GPIO 6: General Purpose I/O # 6
ADC1 : ADC Input Channel 1 (X-)
003
GPIO7 / ADC3
GPIO 7: General Purpose I/O # 7
ADC3 : ADC Input Channel 3 (Y-)
004
GPIO8 / ADC2
GPIO 8: General Purpose I/O # 8
ADC2 : ADC Input Channel 2 (Y+)
005
GPIO9 / ADC0 / MCLK_IN
GPIO 9: General Purpose I/O # 9
ADC0 : ADC Input Channel 0 (X+)
MCLK_IN : Master Clock Input
006
GPIO10
GPIO 10: General Purpose I/O # 10
13.2 POWER STATES
P95020 device has two hardware power states.
OFF State:
P95020 enters OFF state after the first time battery insertion. The system power (VSYS ) is provided by the battery via the
ideal diode. VSYS powering up will issue a power-on-reset to reset all the logic on the device to default state and P95020
enters OFF state. In this state;
32K crystal oscillator (or associate RC oscillator) is running and generates 32k/4k/1k clocks.
The RTC module is enabled and the RTC registers are maintained.
The always on LDO is enabled and provides power to system.
The power switch detection (SW_DET) circuit is running.
Ideal diode driver is running.
All regulators, touch screen controller and audio are in power down or inactive mode.
Wait for interrupts to wake up CPU and bring system to ON state.
ON State:
P95020 enters ON state after momentarily pressing and releasing a button attached to SW_DET or AC adaptor insertion.
The CKGEN (Clock generator module) power is enabled and the 8MHz I2C and processor clock is available.
13.3 POWER SEQUENCING BY EMBEDDED MICROCONTROLLER
Pending embedded uP interrupt will trigger the following actions;
Hardware actions:
Set PSTATE_ON bit of POWER STATE AND SWITCH CONTROL REGISTER (0xA031) to 1, turn on the power
of CKGEN (VDD_CKGEN18, VDD_CKGEN33) and hence 8MHz (processor and I2C clock) clock is available.
Turn on the power of Embedded Microcontroller (VDD_EMBUP18) and release processor reset automatically
after 4ms. Processor start to execute code stroed in the internal ROM or external ROM.
Firmware actions:
Embedded microcontroller (6811) sub-system start with the boot sequence.
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