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參數(shù)資料
| 型號： | P8xC592 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontroller with on-chip CAN |
| 中文描述： | 8位微控制器芯片的CAN |
| 文件頁數(shù)： | 47/108頁 |
| 文件大小： | 650K |
| 代理商： | P8XC592 |
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1996 Jun 27
47
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
Table 57
Description of the other DSCR2 bits
BIT SYMBOL
FUNCTION
4
RTR
Remote Transmission Request
. If the RTR bit is:
HIGH (remote), then the Remote Frame will be transmitted by the CAN-controller.
LOW (data), then the Data Frame will be transmitted by the CAN-controller.
Data Length Code (DLC).
The number of bytes (Data Byte Count) in the Data Field of a message is
coded by the Data Length Code. At the start of a Remote Frame transmission the Data Length Code
is not considered due to the RTR bit being HIGH (remote). This forces the number of
transmitted/received data bytes to be a logic 0. Nevertheless, the Data Length Code must be
specified correctly to avoid bus errors, if two CAN-controllers start a Remote Frame transmission
simultaneously. The range of the Data Byte Count is 0 to 8 bytes and coded as follows:
Data Byte Count
8DLC.3
4DLC.2
2DLC.1
+
+
=
3
2
1
0
DLC.3
DLC.2
DLC.1
DLC.0
.
For reasons of compatibility no Data Byte Counts other than 0,1,2,....8 should be used.
DLC.0
+
13.5.13.2 Data Field
The number of transferred data bytes is determined by the
Data Length Code. The first bit transmitted is the most
significant bit of data byte 1 at address 12.
13.5.14 R
ECEIVE
B
UFFER LAYOUT
The layout of the Receive Buffer and the individual bytes
correspond to the definitions given for the Transmit Buffer
layout, except that the addresses start at 20 instead of 10
(see Fig.15).
13.5.15 H
ANDLING OF THE
CPU-CAN
INTERFACE
Via the four special registers CANADR, CANDAT,
CANCON and CANSTA the CPU has access to the
CAN-controller and also to the DMA-logic. Note that
CANCON and CANSTA have different meanings for a
Read and Write access.
Table 58
The SFRs between CPU and CAN
Reserved bits are read as HIGH. R = Read; W = Write; R/W = Read/Write.
ADDRESS
ACCESS
BIT
7
6
5
4
3
2
1
0
CANADR
DBH
R/W
DMA
Reserved AutoInc
CANA4
CANA3
CANA2
CANA1
CANA0
CANDAT
DAH
R/W
CAND7
CAND6
CAND5
CAND4
CAND3
CAND2
CAND1
CAND0
CANCON; Do not use a RMW instruction
D9H
R
W
Reserved Reserved Reserved WUI
RX0A
RX1A
OI
COS
EI
RRB
TI
AT
RI
TR
WUM
SLP
CANSTA; The bit addresses of CANSTA (7 to 0) are DFH to D8H; do not use a RMW instruction
DFH to D8H R
BS
RAMA7
ES
RAMA6
TS
RAMA5
RS
RAMA4
TCS
RAMA3
TBS
RAMA2
DO
RAMA1
RBS
RAMA0
W
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