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參數(shù)資料
| 型號： | P8xC592 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit microcontroller with on-chip CAN |
| 中文描述： | 8位微控制器芯片的CAN |
| 文件頁數(shù)： | 29/108頁 |
| 文件大?。?/td> | 650K |
| 代理商： | P8XC592 |
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1996 Jun 27
29
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xC592
Table 29
Hardware blocks of the CAN-controller (see Fig.14)
NAME
BLOCK
DESCRIPTION
Interface Management Logic
IML
Interprets commands from the CPU, allocates the message buffers
(TBF, RBF0 and RBF1) and provides interrupts and status information to the
microcontroller.
10 bytes memory into which the CPU writes messages which are to be
transmitted over the CAN network.
RBF0 and RBF1 are each 10 bytes memories which are alternatively used to
store messages received from the CAN network.
The CPU can process one message while another is being received.
Is a sequencer, controlling the data stream between the Transmit Buffer,
Receive Buffers (parallel data) and the CAN-bus (serial data).
Synchronizes the CAN-controller to the bitstream on the CAN-bus.
Controls the output driver.
Performs the error confinement according to the CAN-protocol.
Transmit Buffer
TBF
Receive Buffers (0 and 1)
RBF0
RBF1
Bit Stream Processor
BSP
Bit Timing Logic
Transceiver Control Logic
Error Management Logic
BTL
TCL
EML
Fig.14 Block diagram of the P8xC592 on-chip CAN-controller.
handbook, full pagewidth
MGA159
INTERFACE
MANAGEMENT
LOGIC
TRANSCEIVER
LOGIC
TRANSMIT
BUFFER
BIT TIMING
LOGIC
2
2
ON - CHIP
CAN
CONTROLLER
RECEIVE
BUFFER 0
RECEIVE
BUFFER 1
BIT STREAM
PROCESSOR
ERROR
MANAGEMENT
LOGIC
address
data
CRX0
and
CRX1
CTX0
and
CTX1
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