參數(shù)資料
型號(hào): P8XC557E8
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 67/84頁
文件大?。?/td> 322K
代理商: P8XC557E8
1999 Mar 12
67
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
22 AC CHARACTERISTICS
V
DD
= 5 V
±
10%; V
SS
= 0 V; T
amb
=
40
°
C to +85
°
C; C
L
= 100 pF for Port 0, ALE and PSEN; C
L
= 80 pF for all other
outputs unless otherwise specified; t
clk(min)
= 1/f
clk(max)
(f
clk(max)
= maximum operating frequency); t
clk(min)
= 63 ns.
SYMBOL
PARAMETER
f
clk
= 12 MHz
f
clk
= 16 MHz
VARIABLE CLOCK
f
clk
= 3.5 to 16 MHz
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
External Program Memory;
see Fig.27
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
ALE pulse width
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
address to valid instruction in
PSEN LOW to address float
127
43
53
53
205
0
234
145
59
312
10
85
23
33
33
143
0
150
83
38
208
10
2t
clk
40
t
clk
40
t
clk
30
t
clk
30
3t
clk
45
0
4t
clk
100
3t
clk
105
t
clk
25
5t
clk
105
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External Data Memory;
see Fig.28
t
RLRH
t
WLWH
t
AVLL
t
LLAX
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
RD pulse width
WR pulse width
address valid to ALE LOW
address hold after ALE LOW
RD LOW to valid data in
data hold after RD
data float after RD
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
RD LOW to address float
400
400
43
48
0
200
203
43
33
433
33
252
97
517
585
300
123
0
275
275
23
28
0
138
120
23
13
288
13
148
55
350
398
238
103
0
6t
clk
100
6t
clk
100
t
clk
40
t
clk
35
0
3t
clk
50
4t
clk
130
t
clk
40
t
clk
50
7t
clk
150
t
clk
50
5t
clk
165
2t
clk
70
8t
clk
150
9t
clk
165
3t
clk
+ 50
t
clk
+ 40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UART Timing - Shift Register Mode;
see Fig.30
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
serial port clock cycle time
output data setup to clock rising edge 700
SCL clock frequency
input data hold after clock rising edge 0
clock rising edge to input data valid
1.0
700
0.75
492
8
0
492
12t
clk
10t
clk
133
2t
clk
117
0
10t
clk
133
μ
s
ns
ns
ns
ns
50
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