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參數資料
| 型號： | P8XC557E8 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 47/84頁 |
| 文件大?。?/td> | 322K |
| 代理商： | P8XC557E8 |
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1999 Mar 12
47
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
15.5
Power Control Register (PCON)
PCON is not bit addressable and the value after reset is 00H.
Table 70
Power Control Register (address 87H)
Table 71
Description of PCON bits
7
6
5
4
3
2
1
0
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate
. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
AUX-RAM disable.
When set to logic 1 the internal 1792 bytes AUX-RAM is disabled,
so that all MOVX-Instructions access the external Data Memory - as it is with the
standard 80C51.
RFI-Reduction Mode.
When set to HIGH the toggling of ALE pin is prohibited. This bit
is cleared on reset and can be set and cleared by software. When set, ALE pin will be
pulled down internally, switching an external address latch to a quiet state. See also
Sections 2.1 and 6.2.
Watchdog Load Enable
. This flag must be set by software prior to loading T3
(Watchdog Timer). It is cleared when T3 is loaded.
General purpose flag bits
.
6
ARD
5
RFI
4
WLE
3
2
1
GF1
GF0
PD
Power-down mode select
. Setting this bit activates Power-down mode. It can only be
set if input EW is HIGH.
Idle mode select
. Setting this bit activates the Idle mode.
0
IDL
Fig.16 Idle and Power-down hardware for clock generation.
handbook, full pagewidth
MBH082
PLL
OCSILLATOR
CLOCK
GENERATOR
OCSILLATOR
'second'
timer
32 kHz
PD
XTAL3
XTAL3
SELXTAL1
3.5 to 16 kHz
XTAL2
XTAL1
fclk
IDL
interrupts,
serial
ports
T0, T1, T3
CPU
T2
ADC
PWM
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