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| 型號： | P8XC557E8 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 27/84頁 |
| 文件大?。?/td> | 322K |
| 代理商： | P8XC557E8 |
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1999 Mar 12
27
Philips Semiconductors
Product specification
8-bit microcontroller
P8xC557E8
12.2
Timer T2
Timer T2 is a 16-bit timer/counter which has capture and
compare facilities. The operational diagram is shown in
Figure 11.
The 16 bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with
1
12
of the clock frequency, or
by an external source connected to the T2 input, or it is
switched off. The maximum repetition rate of the external
clock source is
1
12
×
f
clk
, twice that of Timer 0 and Timer 1.
The prescaler is incremented on a rising edge. It is cleared
if its division factor or its input source is changed, or if the
timer/counter is reset (see in Table 31). T2 is readable ‘on
the fly’, without any extra read latches; this means that
software precautions have to be taken against
misinterpretation at overflow from least to most significant
byte while T2 is being read. T2 is not loadable and is reset
by the RST signal or at the positive edge of the input signal
RT2, if enabled. In the Idle or Power-down mode the timer/
counter and prescaler are reset and halted.
T2 is connected to four 16-bit Capture Registers:
CT0, CT1, CT2 and CT3. A rising or falling edge on the
inputs CT0I, CT1I, CT2I or CT3I (alternative function of
Port 1) results in loading the contents of T2 into the
respective Capture Registers and an interrupt request.
Using the Capture Register CTCON (see Table 35), these
inputs may invoke capture and interrupt request on a
positive edge, a negative edge or on both edges. If neither
a positive nor a negative edge is selected for capture input,
no capture or interrupt request can be generated by this
input.
The contents of the Compare Registers CM0, CM1 and
CM2 are continuously compared with the counter value of
Timer T2. When a match occurs, an interrupt may be
invoked. A match of CM0 sets the bits 0 to 5 of Port 4, a
CM1 match resets these bits and a CM2 match toggles bits
6 and 7 of Port 4, provided these functions are enabled by
the STE respectively RTE registers. A match of CM0 and
CM1 at the same time results in resetting bits 0-5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
For more information concerning the TM2CON, CTCON,
TM2IR and the STE/RTE registers see “Data Handbook
IC20; Section 80C51 family hardware description”
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At a byte
overflow of the least significant byte, or at a 16-bit overflow
of the timer/counter, an interrupt sharing the same
interrupt vector is requested. Either one or both of these
overflows can be programmed to request an interrupt.
All interrupt flags must be reset by software.
12.2.1
T2 C
ONTROL
R
EGISTER
(TM2CON)
Table 31
T2 Control Register (address EAH)
Table 32
Description of TM2CON bits
7
6
5
4
3
2
1
0
T2IS1
T2IS0
T2ER
T2BO
T2P1
T2P0
T2MS1
T2MS0
BIT
SYMBOL
DESCRIPTION
7
6
5
T2IS1
T2IS0
T2ER
Timer T2 16-bit overflow interrupt select.
Timer T2 byte overflow interrupt select.
Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising
edge on RT2 (P1.5).
Timer T2 byte overflow interrupt flag.
Timer T2 prescaler select (see Table 33).
4
3
2
1
0
T2BO
T2P1
T2P0
T2MS1
T2MS0
Timer T2 mode select (see Table 34).
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