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參數(shù)資料
| 型號： | P89V664FBC,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 66/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 36 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-2437 935280835557 P89V664FBC |
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P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
69 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.13.1 Idle mode
Idle mode is entered setting the IDL bit in the PCON register. In Idle mode, the program
counter is stopped. The system clock continues to run and all interrupts and peripherals
remain active. The on-chip RAM and the special function registers hold their data during
this mode.
The device exits Idle mode through either a system interrupt or a hardware reset. Exiting
Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle
mode. After exit the Interrupt Service Routine, the interrupted program resumes execution
beginning at the instruction immediately following the instruction which invoked the Idle
mode. A hardware reset starts the device similar to a power-on reset.
6.13.2 Power-down mode
The Power-down mode is entered by setting the PD bit in the PCON register. In the
Power-down mode, the clock is stopped and external interrupts are active for level
sensitive interrupts only. SRAM contents are retained during Power-down, the minimum
VDD level is 2.0 V.
The device exits Power-down mode through either an enabled external level sensitive
interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits
Power-down. Holding the external interrupt pin low restarts the oscillator, the signal must
hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon
interrupt signal restored to logic VIH, the interrupt service routine program execution
resumes beginning at the instruction immediately following the instruction which invoked
Power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of Power-down, the reset or external interrupt should not be executed
before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage
long enough at its normal operating level for the oscillator to restart and stabilize (normally
less than 10 ms).
Table 67.
Power-saving modes
Mode
Initiated by
State of MCU
Exited by
Idle mode
Software (Set IDL bit in
PCON) MOV PCON, #01H
CLK is running. Interrupts,
serial port and timers/counters
are active. Program Counter is
stopped. ALE and PSEN
signals at a HIGH-state during
Idle. All registers remain
unchanged.
Enabled interrupt or hardware reset. Start of
interrupt clears IDL bit and exits Idle mode,
after the ISR RETI instruction, program
resumes execution beginning at the
instruction following the one that invoked
Idle mode. A hardware reset restarts the
device similar to a power-on reset.
Power-down
mode
Software (Set PD bit in
PCON) MOV PCON, #02H
CLK is stopped. On-chip SRAM
and SFR data is maintained.
ALE and PSEN signals at a
LOW-state during power-down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
Enabled external level sensitive interrupt or
hardware reset. Start of interrupt clears PD
bit and exits Power-down mode, after the
ISR RETI instruction program resumes
execution beginning at the instruction
following the one that invoked Power-down
mode. A hardware reset restarts the device
similar to a power-on reset.
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