參數(shù)資料
型號(hào)： P89V664FBC,557
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 62/90頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
65 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.11 Security bits
The security bits protects against software piracy and prevents the contents of the flash
from being read by unauthorized parties in Parallel Programmer mode and ISP mode.
Since the end application might need to erase pages and read from the code memory, the
security bits have no effect in IAP mode. However, the security bits’ programmed/erased
state may be read using IAP function calls allowing the end user code to limit access, if
desired. The security bits and their effects are shown in Table 53.
Note: On this device MOVC instructions executed from external code memory are
disabled from fetching code bytes from internal code memory.
6.12 Interrupt priority and polling sequence
The device supports eight interrupt sources under a four level priority scheme. Table 54
summarizes the polling sequence of the supported interrupts. Note that the SPI serial
interface and the UART share the same interrupt vector. (See Figure 32).
Table 53.
Security bit functions
Security bit
Description
1
Write protect. When programmed, prohibits further erasing or
programming, except to program other security bits or a chip erase.
2
Read protect. When programmed inhibits reading of user code memory.
3
External execution inhibit. When programmed prevents any execution of
instructions from external code memory.
Table 54.
Interrupt polling sequence
Description
Interrupt flag
Vector address Interrupt
enable
Interrupt
priority
Service
priority
Wake-up
Power-down
External
Interrupt 0
IE0
0003H
EX0
PX0/H
1 (highest)
yes
T0
TF0
000BH
ET0
PT0/H
3
no
External
Interrupt 1
IE1
0013H
EX1
PX1/H
4
yes
T1
TF1
001BH
ET1
PT1/H
5
no
UART
TI/RI
0023H
ES0
PS0/H
6
no
I2C-bus
(primary)
-
002BH
ES1
PS1/H
2
no
PCA
CF/CCFn
0033H
EC
PPCH
8
no
T2
TF2, EXF2
003BH
ET2
PT2/H
7
no
I2C-bus
(secondary)
-
0043H
ES2
PS2/H
10
no
SPI
SPIF
004BH
ES3
PS3/H
9
no
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