參數(shù)資料
型號： P89V664FBC,557
廠商： NXP Semiconductors
文件頁數(shù)： 12/90頁
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
2 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
Idle mode
2.3 Comparison to the P89C660/662/664 devices
SPI interface. The P89V660/662/664 devices include an SPI interface that was not
present on the P89C660/662/664 devices.
Dual I2C-bus interfaces. The P89V660/662/664 devices have two I2C-bus interfaces.
The P89C660/662/664 devices have one.
More I/O pins. The P89V660/662/664 devices have an additional four-bit I/O port,
Port 4.
The 6x/12x mode on theP89V660/662/664 devices is programmable and erasable
using ISP and IAP as well as parallel programmer mode. The P89C660/662/664
devices could only be switched using parallel programmer mode.
Smaller block sizes. The smallest block size on the P89C660/662/664 devices was
8 kB. The P89V660/662/664 devices have a page size of 128 B. These small pages
can be erased and reprogrammed using IAP function calls making use of the code
memory for non-volatile data storage practical. Each page erase is 30 ms or less. The
IAP and ISP code in P89V660/662/664 devices support these 128-byte page
operations. In addition, the IAP and ISP code uses multiple page erase operations to
emulate the erasing of the larger block sizes (8 kB and 16 kB to maintain firmware
compatibility).
Status bit versus Status byte. The P89V660/662/664 devices used a Status byte to
control the automatic entry into ISP mode following a reset. On the P89V660/662/664
devices this has changed to a single Status bit. Since the ISP entry was based on the
zero/non-zero value of the Status byte this is an almost identical operation on the
P89V660/662/664 devices.
Faster block erase. The erase time for the entire user code memory of the
P89V660/662/664 devices is 150 ms.
3.
Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
P89V662FA
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
P89V662FBC
TQFP44
plastic thin quad flat package; 44 leads; body
10
10 1.0 mm
SOT376-1
P89V664FA
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
P89V664FBC
TQFP44
plastic thin quad flat package; 44 leads; body
10
10 1.0 mm
SOT376-1
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