參數(shù)資料
型號(hào)： P89V664FBC,557
廠(chǎng)商： NXP Semiconductors
文件頁(yè)數(shù)： 24/90頁(yè)
文件大小： 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱(chēng)： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
30 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.4.5.3
Slave receiver mode
In the Slave Receiver mode, data bytes are received from a master transmitter. To
initialize the Slave Receiver mode, the user should write the slave address to the Slave
Address Register (S1ADR) and the I2C-bus Control Register (S1CON) should be
configured as follows:
CR2:0 are not used for slave mode. ENS1 must be set = 1 to enable I2C-bus function. AA
bit must be set = 1 to acknowledge its own slave address or the general call address.
STA, STO and SI are cleared to 0.
After S1ADR and S1CON are initialized, the interface waits until it is addressed by its own
address or general address followed by the data direction bit which is 0(W). If the direction
bit is 1(R), it will enter Slave Transmitter mode. After the address and the direction bit
have been received, the SI bit is set and a valid status code can be read from the Status
Register(S1STA). Refer to Table 25 for the status codes and actions.
6.4.5.4
Slave transmitter mode
The first byte is received and handled as in the Slave Receiver mode. However, in this
mode, the direction bit will indicate that the transfer direction is reversed. Serial data is
transmitted via P1[7]/SDA while the serial clock is input through P1[6]/SCL. START and
Fig 10. A Master Receiver switches to Master Transmitter after sending Repeated Start
S
R
A
SLA
logic 0 = write
logic 1 = read
from master to slave
from slave to master
002aaa931
DATA
data transferred
(n Bytes + acknowledge)
A
W
A
SLA
DATA
A
P
A
RS
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
SLA = slave address
RS = repeat START condition
Table 21.
I2C-bus control register (S1CON - address D8H)
Bit
7
6
5
4
3
2
1
0
Symbol
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
Value
-
100
01-
-
Fig 11. Format of slave receiver mode
S
W
A
slave address
logic 0 = write
logic 1 = read
from master to slave
from slave to master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
RS = repeated START condition
002aaa932
DATA
data transferred
(n Bytes + acknowledge)
A
A/A
P/RS
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