參數(shù)資料
型號： P89V664FBC,557
廠商： NXP Semiconductors
文件頁數(shù)： 39/90頁
文件大小： 0K
描述： IC 80C51 MCU FLASH 64K 44-TQFP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準包裝： 800
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 706 (CN2011-ZH PDF)
配用： 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱： 568-2437
935280835557
P89V664FBC
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
44 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
6.6.1 Capture mode
In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which
upon overflowing sets bit TF2, the Timer 2 overflow bit.
The capture mode is illustrated in Figure 18.
This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the
IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added
feature that a 1- to -0 transition at external input T2EX causes the current value in the
Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively.
In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like
TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow
interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to
determine which event caused the interrupt.
There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs
from T2EX, the counter keeps on counting T2 pin transitions or fosc / 6 pulses. Since once
loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2
interrupt is signalled it has to be serviced before new capture event on T2EX pin occurs.
Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from
TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to
previously reported interrupt.
Table 35.
T2MOD - Timer 2 mode control register (address C9H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
T2OE
Timer 2 Output Enable bit. Used in programmable clock-out mode
only.
0
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be configured
as an up/down-counter.
Fig 18. Timer 2 in Capture mode
002aaa523
OSC
÷6
T2 pin
C/T2 = 0
C/T2 = 1
TL2
(8-bits)
TH2
(8-bits)
TF2
control
capture
TR2
timer 2
interrupt
EXF2
RCAP2L RCAP2H
control
EXEN2
transition
detector
T2EX pin
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