參數(shù)資料
型號(hào)： P89V51RD2
廠商： NXP Semiconductors N.V.
英文描述： 8-bit 80C51 5 V low power 64 kB Flash microcontroller with 1 kB RAM
中文描述： 8位80C51的5 V低功耗64 kB閃存1 KB RAM內(nèi)存控制器
文件頁數(shù)： 45/77頁
文件大?。?/td> 350K
代理商： P89V51RD2
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
45 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
To protect the system against software deadlock, the user software must refresh the
WDT within a user-defined time period. If the software fails to do this periodical
refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The
software can be designed such that the WDT times out if the program does not work
properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a Watchdog timer. The WDT register
will increment every 344,064 crystal clocks. The upper 8-bits of the time base register
(WDTD) are used as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 20
provides a block diagram of the WDT. Two SFRs (WDTC and WDTD)
control Watchdog timer operation. During idle mode, WDT operation is temporarily
suspended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255
WDTD)
×
344064
×
1/f
CLK (XTAL1)
where WDTD is the value loaded into the WDTD register and f
osc
is the oscillator
frequency.
Fig 20. Block diagram of programmable Watchdog timer
002aaa531
WDT
UPPER BYTE
WDT reset
internal reset
344064
clks
COUNTER
CLK (XTAL1)
external RST
WDTC
WDTD
Table 35:
Bit addressable; Reset value: 00H
Bit
7
Symbol
-
WDTC - Watchdog control register (address COH) bit allocation
6
-
5
-
4
3
2
1
0
WDOUT
WDRE
WDTS
WDT
SWDT
Table 36:
Bit
7 to 5
4
WDTC - Watchdog control register (address COH) bit description
Symbol
Description
-
Reserved for future use. Should be set to
‘0’
by user programs.
WDOUT
Watchdog output enable. When this bit and WDRE are both set, a
Watchdog reset will drive the reset pin active for 32 clocks.
WDRE
Watchdog timer reset enable. When set enables a Watchdog timer
reset.
3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P89V51RD2BN 制造商:NXP Semiconductors 功能描述:IC MCU 8BIT 80C51 64K FLASH DIP40 制造商:NXP Semiconductors 功能描述:IC, MCU 8BIT 80C51 64K FLASH, DIP40
P89V51RD2BN,112 功能描述:8位微控制器 -MCU 80C51 5V 16/32/64KB FLASH MCU 1 KB RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89V51RD2FA 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 64K FLASH PLCC44
P89V51RD2FA,512 功能描述:8位微控制器 -MCU 80C51 64K FL / 1K RM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
P89V51RD2FA512 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 40MHZ LCC-44
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