參數(shù)資料
型號: P89V51RD2
廠商: NXP Semiconductors N.V.
英文描述: 8-bit 80C51 5 V low power 64 kB Flash microcontroller with 1 kB RAM
中文描述: 8位80C51的5 V低功耗64 kB閃存1 KB RAM內(nèi)存控制器
文件頁數(shù): 28/77頁
文件大?。?/td> 350K
代理商: P89V51RD2
Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Product data
Rev. 03 — 02 December 2004
28 of 77
9397 750 14341
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 14:
Not bit addressable; Reset value: 00000000B; Reset source(s): any source
Bit
7
6
5
Symbol
T1GATE
T1C/T
T1M1
TMOD - Timer/Counter mode control register (address 89H) bit allocation
4
3
2
1
0
T1M0
T0GATE
T0C/T
T0M1
T0M0
Table 15:
Bit
TMOD - Timer/Counter mode control register (address 89H) bit description
Symbol
Description
T1/T0
Bits controlling Timer1/Timer0
GATE
Gating control when set. Timer/Counter ‘x’ is enabled only while
‘INTx’ pin is HIGH and ‘TRx’ control pin is set. When cleared,
Timer ‘x’ is enabled whenever ‘TRx’ control bit is set.
C/T
Gating Timer or Counter Selector cleared for Timer operation
(input from internal system clock.) Set for Counter operation (input
from ‘Tx’ input pin).
Table 16:
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
M0
Operating mode
0
0
8048 timer ‘TLx’ serves as 5-bit prescaler
1
1
16-bit Timer/Counter ‘THx’ and ‘TLx' are
cascaded; there is no prescaler.
0
2
8-bit auto-reload Timer/Counter ‘THx’ holds a
value which is to be reloaded into ‘TLx’ each
time it overflows.
1
3
(Timer 0) TL0 is an 8-bit Timer/Counter
controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1
control bits.
1
3
(Timer 1) Timer/Counter 1 stopped.
M1
0
0
1
1
1
Table 17:
Bit addressable; Reset value: 00000000B; Reset source(s): any reset
Bit
7
6
Symbol
TF1
TR1
TCON - Timer/Counter control register (address 88H) bit allocation
5
4
3
2
1
0
TF0
TR0
IE1
IT1
IE0
IT0
Table 18:
Bit
7
TCON - Timer/Counter control register (address 88H) bit description
Symbol
Description
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 1
Interrupt routine, or by software.
TR1
Timer 1 Run control bit. Set/cleared by software to turn
Timer/Counter 1 on/off.
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.
Cleared by hardware when the processor vectors to Timer 0
Interrupt routine, or by software.
TR0
Timer 0 Run control bit. Set/cleared by software to turn
Timer/Counter 0 on/off.
6
5
4
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