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參數(shù)資料
型號: P89V51RB2FN,112
廠商: NXP Semiconductors
文件頁數(shù): 58/80頁
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 40-DIP
產品培訓模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 216
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-3229-5
935278707112
P89V51RB2FN
2009-2011 Microchip Technology Inc.
DS39960D-page 61
PIC18F87K22 FAMILY
Clocks to the device continue while the INTOSC source
stabilizes after an interval of TIOBST (Parameter 39,
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4
Q3
Q2
OSC1
Peripheral
Program
Q1
LF-INTOSC
Q1
Counter
Clock
CPU
Clock
PC + 2
PC
123
n-1
n
Clock Transition(1)
Q4
Q3
Q2
Q1
Q3
Q2
PC + 4
Note 1:
Clock transition typically occurs within 2-4 TOSC.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 2
Clock
Counter
Q2
Q3
Note 1:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2:
Clock transition typically occurs within 2-4 TOSC.
SCS<1:0> bits Changed
TPLL(1)
12
n-1 n
Clock
OSTS bit Set
Transition(2)
Multiplexer
TOST(1)
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