參數(shù)資料
型號: P89V51RB2FN,112
廠商: NXP Semiconductors
文件頁數(shù): 21/80頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 40-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝: 216
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-3229-5
935278707112
P89V51RB2FN
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
28 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 14.
TMOD - Timer/counter mode control register (address 89H) bit allocation
Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source
Bit
7
6
5
4
3
2
1
0
Symbol
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
Table 15.
TMOD - Timer/counter mode control register (address 89H) bit description
Bit
Symbol
Description
T1/T0
Bits controlling Timer1/Timer0
GATE
Gating control when set. Timer/counter ‘x’ is enabled only while ‘INTx’
pin is HIGH and ‘TRx’ control pin is set. When cleared, Timer ‘x’ is
enabled whenever ‘TRx’ control bit is set.
C/T
Gating Timer or Counter Selector cleared for Timer operation (input
from internal system clock.) Set for Counter operation (input from ‘Tx’
input pin).
Table 16.
TMOD - Timer/counter mode control register (address 89H) M1/M0 operating
mode
M1
M0
Operating mode
0
8048 timer ‘TLx’ serves as 5-bit prescaler
0
1
16-bit Timer/counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
1
0
2
8-bit auto-reload Timer/counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it
overows.
1
3
(Timer 0) TL0 is an 8-bit Timer/counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit
timer only controlled by Timer 1 control bits.
1
3
(Timer 1) Timer/counter 1 stopped.
Table 17.
TCON - Timer/counter control register (address 88H) bit allocation
Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset
Bit
7
6
5
4
3
2
1
0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 18.
TCON - Timer/counter control register (address 88H) bit description
Bit
Symbol
Description
7
TF1
Timer 1 overow ag. Set by hardware on Timer/counter overow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/counter
1 on/off.
5
TF0
Timer 0 overow ag. Set by hardware on Timer/counter overow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/counter
0 on/off.
3
IE1
Interrupt 1 Edge ag. Set by hardware when external interrupt 1
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
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