參數(shù)資料
型號: P89V51RB2FN,112
廠商: NXP Semiconductors
文件頁數(shù): 22/80頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 40-DIP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝: 216
系列: 89V
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁面: 706 (CN2011-ZH PDF)
配用: 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP
其它名稱: 568-3229-5
935278707112
P89V51RB2FN
P89V51RB2_RC2_RD2_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
29 of 80
NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
6.4.1 Mode 0
Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a xed divide-by-32 prescaler. Figure 8 shows mode 0 operation.
In this mode, the Timer register is congured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt ag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the Special Function Register TCON (Figure 7). The GATE bit is in the TMOD
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run ag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 8). There are two
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
6.4.2 Mode 1
Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See Figure 9.
2
IT1
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 1.
1
IE0
Interrupt 0 Edge ag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
0
IT0
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 0.
Table 18.
TCON - Timer/counter control register (address 88H) bit description …continued
Bit
Symbol
Description
Fig 8.
Timer/counter 0 or 1 in mode 0 (13-bit counter)
002aaa519
osc/6
Tn pin
TRn
TnGate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
overflow
interrupt
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