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參數(shù)資料
| 型號： | P89V51RB2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 53/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 16K 40-DIP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名稱： | 568-3229-5 935278707112 P89V51RB2FN |
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2009-2011 Microchip Technology Inc.
DS39960D-page 57
PIC18F87K22 FAMILY
4.0
POWER-MANAGED MODES
The PIC18F87K22 family of devices offers a total of
seven operating modes for more efficient power man-
agement. These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (such as battery-powered
devices).
There are three categories of power-managed mode:
Run modes
Idle modes
Sleep mode
There is an Ultra Low-Power Wake-up (ULPWU) for
waking from the Sleep mode.
These categories define which portions of the device
are clocked, and sometimes, at what speed. The Run
and Idle modes may use any of the three available
clock sources (primary, secondary or internal oscillator
block). The Sleep mode does not use a clock source.
The ULPWU mode, on the RA0 pin, enables a slow fall-
ing voltage to generate a wake-up, even from Sleep,
without excess current consumption. (See Section 4.7
The power-managed modes include several power-
saving features offered on previous PIC devices. One
is the clock switching feature, offered in other PIC18
devices. This feature allows the controller to use the
SOSC oscillator instead of the primary one. Another
power-saving feature is Sleep mode, offered by all PIC
devices, where all device clocks are stopped.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions:
Will the CPU be clocked or not
What will be the clock source
The IDLEN bit (OSCCON<7>) controls CPU clocking,
while the SCS<1:0> bits (OSCCON<1:0>) select the
clock source. The individual modes, bit settings, clock
sources and affected modules are summarized in
4.1.1
CLOCK SOURCES
The SCS<1:0> bits select one of three clock sources
for power-managed modes. Those sources are:
The primary clock as defined by the FOSC<3:0>
Configuration bits
The secondary clock (the SOSC oscillator)
The internal oscillator block (for LF-INTOSC
modes)
4.1.2
ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is used. Changing these bits
causes an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These considerations
are discussed in Section 4.1.3 “Clock Transitions
and subsequent sections.
Entering the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current and impending mode, a
change to a power-managed mode does not always
require setting all of the previously discussed bits. Many
transitions can be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured as
desired, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 4-1:
POWER-MANAGED MODES
Mode
OSCCON Bits
Module Clocking
Available Clock and Oscillator Source
IDLEN<7>(1)
SCS<1:0>
CPU
Peripherals
Sleep
0
N/A
Off
None – All clocks are disabled
PRI_RUN
N/A
00
Clocked
Primary – XT, LP, HS, EC, RC and PLL modes.
This is the normal, Full-Power Execution mode.
SEC_RUN
N/A
01
Clocked
Secondary – SOSC Oscillator
RC_RUN
N/A
1x
Clocked
Internal oscillator block(2)
PRI_IDLE
100
Off
Clocked
Primary – LP, XT, HS, RC, EC
SEC_IDLE
101
Off
Clocked
Secondary – SOSC oscillator
RC_IDLE
11x
Off
Clocked
Internal oscillator block(2)
Note 1:
IDLEN reflects its value when the SLEEP instruction is executed.
2:
Includes INTOSC (HF-INTOSC and MG-INTOSC) and INTOSC postscaler, as well as the LF-INTOSC
source.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P89V51RC2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM |
| P89V51RC2BN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM |
| P89V51RC2FA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM |
| P89V51RC2FA,512 | 功能描述:8位微控制器 -MCU 80C51 32K FL / 512 R RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P89V51RC2FBC | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM |
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