參數(shù)資料
型號: P89LPC9103FTK
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO10
封裝: 3 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-229, SOT-650-1, HVSON-10
文件頁數(shù): 43/58頁
文件大小: 257K
代理商: P89LPC9103FTK
9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
43 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
9.3 Block diagram
9.4 A/D operating modes
9.4.1
Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be
performed and the result placed in the result register which corresponds to the selected
input channel. An interrupt, if enabled, will be generated after the conversion completes.
9.4.2
Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the
conversions will be sequentially placed in the four result registers. An interrupt, if enabled,
will be generated after every four conversions. Additional conversion results will again
cycle through the four result registers, overwriting the previous results. Continuous
conversions continue until terminated by the user.
9.4.3
Auto scan, single conversion mode
Any combination of the four input channels can be selected for conversion. A single
conversion of each selected input will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will be
generated after all selected channels have been converted. If only a single channel is
selected this is equivalent to single channel, single conversion mode.
9.4.4
Auto scan, continuous conversion mode
Any combination of the four input channels can be selected for conversion. A conversion
of each selected input will be performed and the result placed in the result register which
corresponds to the selected input channel. An interrupt, if enabled, will be generated after
all selected channels have been converted. The process will repeat starting with the first
selected channel. Additional conversion results will again cycle through the four result
registers, overwriting the previous results. Continuous conversions continue until
terminated by the user.
Fig 17. ADC block diagram.
+
comp
DAC1
SAR
8
INPUT
MUX
CONTROL
LOGIC
CCLK
002aaa975
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