參數(shù)資料
型號(hào): P89LPC9103FTK
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO10
封裝: 3 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-229, SOT-650-1, HVSON-10
文件頁(yè)數(shù): 21/58頁(yè)
文件大小: 257K
代理商: P89LPC9103FTK
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P89LPC9103 special function registers
…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
MSB
9
P
R
2
P
P
8
[1]
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
[2]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]
All ports are in input-only (high-impedance) state after power-up.
[4]
The RSTSRC register reflects the cause of the P89LPC9102/9103/9107 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx110000.
[5]
The only reset source that affects these SFRs is power-on reset.
[6]
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[7]
After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1s, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog timer reset and is logic 0 after power-on
reset. Other resets will not affect WDTOF.
WDL
WFEED1
WFEED2
Watchdog load
Watchdog feed 1
Watchdog feed 2
C1h
C2h
C3h
FF
11111111
Table 8:
Bit functions and addresses
Reset value
Hex
LSB
Binary
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