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參數(shù)資料
| 型號： | P89LPC9103FTK |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter |
| 中文描述： | 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO10 |
| 封裝： | 3 X 3 MM, 0.85 MM HEIGHT, PLASTIC, MO-229, SOT-650-1, HVSON-10 |
| 文件頁數(shù)： | 39/58頁 |
| 文件大?。?/td> | 257K |
| 代理商： | P89LPC9103FTK |
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9397 750 14655
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
39 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog timer feature is disabled, it can be used as an interval
timer and may generate an interrupt.
Figure 16
shows the watchdog timer in Watchdog
mode. Feeding the watchdog timer requires a two-byte sequence. If PCLK is selected as
the watchdog timer clock and the CPU is powered-down, the watchdog timer is disabled.
The watchdog timer has a time-out period that ranges from a few
μ
s to a few seconds.
Please refer to the P89LPC9102/9103/9107 User manualfor more details.
8.25 Additional features
8.25.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog timer reset had occurred. Care should be taken when
writing to AUXR1 to avoid accidental software resets.
8.25.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
(1) Watchdog timer reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by
a feed sequence.
Fig 16. Watchdog timer in Watchdog mode (WDTE = 1).
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aaa980
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
PCLK
÷
32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset (1)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC9103FTK,115 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC9107 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable flash with 8-bit A/D converter |
| P89LPC9107FDH | 制造商:NXP Semiconductors 功能描述:MCU 8BIT 80C51 1K FLASH TSSOP14 |
| P89LPC9107FDH,129 | 功能描述:8位微控制器 -MCU 80C51 1K FL 128B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC9107FDH129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-14 |
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