參數(shù)資料
型號(hào): P83C591SFA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 8-bit microcontroller with CAN controller
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, SOT-187-2, LCC-44
文件頁數(shù): 46/161頁
文件大?。?/td> 588K
代理商: P83C591SFA
1999 Aug 19
46
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5.14 E
RROR
W
ARNING
L
IMIT
R
EGISTER
(EWLR)
The Error Warning Limit could be defined within this register. The default value (after hardware reset) is 96d. In Reset
Mode this register appears to the CPU as a read / write memory.
Table 28
Error Warning Limit Register (EWLR) (CAN address 13)
Note that a content change of the EWL-Register is possible only, if the Reset Mode was entered previously. An Error
Status change (Status Register) and an Error Warning Interrupt forced by the new register content will not occur, until
the Reset Mode is cancelled again.
12.5.15 RX E
RROR
C
OUNTER
R
EGISTER
(RXERR)
The RX Error Counter Register reflects the current value of the Receive Error Counter. After hardware reset this register
is initialised to “0”. In Operating Mode this register appears to the CPU as a read only memory. A write access to this
register is possible only in Reset Mode.
If a Bus Off event occurs, the RX Error counter is initialised to “0”. As long as Bus Off is valid, writing to this register has
no effect.
Table 29
RX Error Counter Register (RXERR) (CAN address 14)
Note that a CPU-forced content change of the RX Error Counter is possible only, if the Reset Mode was entered
previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new
register content will not occur, until the Reset Mode is cancelled again.
7
6
5
4
3
2
1
0
EWL.7
EWL.6
EWL.5
EWL.4
EWL.3
EWL.2
EWL.1
EWL.0
7
6
5
4
3
2
1
0
RXERR.7
RXERR.6
RXERR.5
RXERR.4
RXERR.3
RXERR.2
RXERR.1
RXERR.0
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