參數(shù)資料
型號(hào): P83C591SFA
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 8-bit microcontroller with CAN controller
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, SOT-187-2, LCC-44
文件頁數(shù): 126/161頁
文件大?。?/td> 588K
代理商: P83C591SFA
1999 Aug 19
126
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
otherwise the bit being tested is cleared. This process is
repeated until all ten bits have been tested, at which stage
the result of the conversion is held in the successive
approximation register. Figure 48 shows a conversion flow
chart. The bit pointer identifies the bit under test. The
conversion takes four machine cycles per bit.
The end of the 10-bit conversion is flagged by control bit
ADCON.4 (ADCI). The upper 8 bits of the result are held in
Special Function Register ADCH, and the two remaining
bits are held in ADCON.7 (ADC.1) and ADCON.6 (ADC.0).
The user may ignore the two least significant bits in
ADCON and use the ADC as an 8-bit converter (8 upper
bits in ADCH). In any event, the total actual conversion
time is 50 machine cycles for the P8xC591. ADCI will be
set and the ADCS status flag will be reset 50 (or 24) cycles
after the command flip-flop (ADCS) is set.
Control bits ADCON.0, ADCON.1, and ADCON.2 are used
to control an analog multiplexer which selects one of six
analog channels (see Section 20.3.1). An ADC conversion
in progress is unaffected by a new software ADC start. The
result of a completed conversion remains unaffected
provided ADCI = logic 1; a new ADC conversion already in
progress is aborted when the Idle or Power-down mode is
entered. The result of a completed conversion (ADCI =
logic 1) remains unaffected when entering the Idle mode.
Fig.49 Successive Approximation ADC.
handbook, full pagewidth
MHI051
SUCCESSIVE
APPROXIMATION
REGISTER
DAC
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
START
STOP
Vin
VDAC
full scale
t/tau
VDAC
1/2
3/4
7/8
15/16
29/32
59/64
1
1
0
2
3
4
5
6
Vin
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