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| 型號(hào)： | P83C591SFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Single-chip 8-bit microcontroller with CAN controller |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, SOT-187-2, LCC-44 |
| 文件頁(yè)數(shù)： | 32/161頁(yè) |
| 文件大小： | 588K |
| 代理商： | P83C591SFA |
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1999 Aug 19
32
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
12.5
CAN Registers
12.5.1
R
ESET
V
ALUES
Detection of a set Reset Mode bit results in aborting the current transmission / reception of a message and entering the
Reset Mode. On the ‘1’-to-’0’ transition of the Reset Mode bit, the CAN Controller returns to the mode defined within the
Mode Register.
Table 12
Reset mode configuration
“X” means that the values of these registers or bits are not influenced.
ADDR.
REGISTER
BIT
SYMBOL
NAME
RESET BY
HARDWARE
SETTING MOD.0 BY
SOFTWARE OR
DUE TO BUS-OFF
0
Mode
MOD.7
MOD.6
MOD.5
MOD.4
MOD.3
MOD.2
MOD.1
MOD.0
TM
RIPM
RPM
SM
-
STM
LOM
RM
Test Mode
Receive Interrupt Pulse Mode
Receive Polarity Mode
Sleep Mode
-
Self Test Mode
Listen Only Mode
Reset Mode
0 (disabled)
X no change
0 (active low)
0 (wake-up)
0 (reserved)
0 (normal)
0 (normal)
1 (present)
0 (disabled)
X no change
0 (active high)
0 (wake-up)
0 (reserved)
X no change
X no change
1 (present)
1
Command
CMR.7-5
CMR.4
CMR.3
CMR.2
CMR.1
CMR.0
-
SRR
CDO
RRB
AT
TR
-
Self Reception Request
Clear Data Overrun
Release Receive Buffer
Abort Transmission
Transmission Request
0 (reserved)
0 (absent)
0 (no action)
0 (no action)
0 (absent)
0 (absent)
0 (reserved)
0 (absent)
0 (no action)
0 (no action)
0 (absent)
0 (absent)
2
Status
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
BS
ES
TS
RS
TCS
TBS
DOS
RBS
Bus Status
Error Status
Transmit Status
Receive Status
Transmission Complete Status
Transmit Buffer Status
Data Overrun Status
Receive Buffer Status
0 (Bus-On)
0 (ok)
1 (wait idle)
1 (wait idle)
1 (complete)
1 (released)
0 (absent)
0 (empty)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
X no change
(1)
0 (reset)
0 (reset)
3
Interrupt
IR.7
IR.6
IR.5
IR.4
IR.3
IR.2
IR.1
IR.0
BEI
ALI
EPI
WUI
DOI
EI
TI
RI
Bus Error Interrupt
Arbitration Lost Interrupt
Error Passive Interrupt
Wake-Up Interrupt
Data Overrun Interrupt
Error Warning Interrupt
Transmit Interrupt
Receive Interrupt
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
X no change
(1)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
X no change
0 (reset)
0 (reset)
4
Interrupt Enable
IER.7
IER.6
IER.5
IER.4
IER.3
IER.2
IER.1
IER.0
BEIE
ALIE
EPIE
WUIE
DOIE
EIE
TIE
RIE
Bus Error Interrupt Enable
Arbitr. Lost Interrupt Enable
Error Passive Interrupt
Wake-Up Interrupt Enable
Data Overrun Interrupt Enable
Error Warning Interrupt Enable
Transmit Interrupt Enable
Receive Interrupt Enable
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
5
Rx Interrupt Level
-
RIL
Rx Interrupt Level
00000000b
X no change
6
Bus Timing 0
BTR0.7
BTR0.6
BTR0.5
BTR0.4
BTR0.3
BTR0.2
BTR0.1
BTR0.0
SJW.1
SJW.0
BRP.5
BRP.4 BRP.3
BRP.2
BRP.1 BRP.0
Synchronization Jump Width 1
Synchronization Jump Width 0
Baud Rate Prescaler 5
Baud Rate Prescaler 4
Baud Rate Prescaler 3
Baud Rate Prescaler 2
Baud Rate Prescaler 1
Baud Rate Prescaler 0
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
7
Bus Timing 1
BTR1.7
BTR1.6
BTR1.5
BTR1.4
BTR1.3
BTR1.2
BTR1.1
BTR1.0
SAM
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
Sampling
Time Segment 2.2
Time Segment 2.1
Time Segment 2.0
Time Segment 1.3
Time Segment 1.2
Time Segment 1.1
Time Segment 1.0
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
X no change
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