參數(shù)資料
型號(hào)： P83C591SFA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Single-chip 8-bit microcontroller with CAN controller
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, SOT-187-2, LCC-44
文件頁數(shù)： 35/161頁
文件大小： 588K
代理商： P83C591SFA
1999 Aug 19
35
Philips Semiconductors
Objective Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
3.
This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The
Listen Only Mode can be used e.g. for software driven bit rate detection and “hot plugging”.
During a Hardware reset or when the Bus Status bit is set ‘1’ (Bus-Off), the Reset Mode bit is set ‘1’ (present). During
an external reset the CPU cannot set the Reset Mode bit ‘0’ (absent). Therefore, after having set the Reset Mode bit
‘0’, the CPU must check this bit to ensure that the external reset pin is not being held HIGH. After the Reset Mode
bit is set ‘0’ the CAN Controller will wait for:
a) one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by Hardware reset
or a CPU-initiated reset.
b) 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off,
before re-entering the Bus-On mode
4.
12.5.3
C
OMMAND
R
EGISTER
(CMR)
The contents of the Command Register are used to change the behaviour of the CAN Controller. Control bits may be set
or reset by the CPU which uses the Command Register as a read/write memory.
Table 14
Command Register (CMR) CAN Addr. 1, bit interpretation
Notes
1.
Upon Self Reception Request a message is transmitted and simultaneously received if the acceptance filter is set to
the corresponding identifier. A receive and a transmit interrupt will indicate correct self reception. (see also Self Test
Mode in Mode Register).
This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as
the Data Over run Status bit is set no further Data Overrun Interrupt is generated.
After reading the contents of the Receive Buffer, the CPU can release this memory space of the RXFIFO by setting
the Release Receive Buffer bit ‘1’. This may result in another message becoming immediately available within the
Receive Buffer. If there is no other message available, the Receive Interrupt bit is reset. The Receive Interrupt is also
reset in case there is no “high priority” message available within the FIFO (see acceptance filter description) and the
available message bytes are equal to or less to the specified value within the Receive Interrupt Level Register. If the
RRB command is given, it will take at least 2 internal clock cycles before a new receive interrupt is generated and
Rx Buffer Start Address is updated.
2.
3.
BIT
SYMBOL
NAME
VALUE
FUNCTION
CMR.7
to
CMR.5
CMR.4
-
reserved
-
SRR
Self Reception Request;
Notes 1 and 6
1 (present)
A message shall be transmitted and received
simultaneously.
0 (absent)
1 (clear)
0 (no action)
1 (released)
CMR.3
CDO
Clear Data Overrun;
Note 2
The Data Overrun Status bit is cleared.
CMR.2
RRB
Release Receive Buffer;
Note 3
The Receive Buffer, representing the message
memory space in the RXFIFO is released.
0 (no action)
1 (present)
CMR.1
AT
Abort Transmission;
Notes 4 and 6
If not already in progress, a pending Transmission
Request is cancelled.
0 (absent)
1 (present)
0 (absent)
CMR.0
TR
Transmission Request;
Notes 5 and 6
A message shall be transmitted.
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