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參數(shù)資料
| 型號(hào)： | P82C55A |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS PROGRAMMABLE PERIPHERAL INTERFACE |
| 中文描述： | 24 I/O, PIA-GENERAL PURPOSE, PDIP40 |
| 封裝： | DIP-40 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 325K |
| 代理商： | P82C55A |
82C55A
Table 1. Pin Description
Symbol
Pin Number
Dip
Type
Name and Function
PLCC
PA
3–0
1–4
2–5
I/O
PORT A, PINS 0–3:
Lower nibble of an 8-bit data output latch/
buffer and an 8-bit data input latch.
RD
5
6
I
READ CONTROL:
This input is low during CPU read operations.
CS
6
7
I
CHIP SELECT:
A low on this input enables the 82C55A to
respond to RD and WR signals. RD and WR are ignored
otherwise.
GND
7
8
System Ground
A
1–0
8–9
9–10
I
ADDRESS:
These input signals, in conjunction RD and WR,
control the selection of one of the three ports or the control
word registers.
A
1
0
A
0
0
RD
WR
CS
Input Operation (Read)
0
1
0
Port A - Data Bus
0
1
0
1
0
Port B - Data Bus
1
0
0
1
0
Port C - Data Bus
1
1
0
1
0
Control Word - Data Bus
Output Operation (Write)
0
0
1
0
0
Data Bus - Port A
0
1
1
0
0
Data Bus - Port B
1
0
1
0
0
Data Bus - Port C
1
1
1
0
0
Data Bus - Control
Disable Function
X
X
X
X
1
Data Bus - 3 - State
X
X
1
1
0
Data Bus - 3 - State
PC
7–4
10–13
11,13–15
I/O
PORT C, PINS 4–7:
Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input buffer (no latch for input). This port
can be divided into two 4-bit ports under the mode control. Each
4-bit port contains a 4-bit latch and it can be used for the control
signal outputs and status signal inputs in conjunction with ports
A and B.
PC
0–3
PB
0-7
14–17
16–19
I/O
PORT C, PINS 0–3:
Lower nibble of Port C.
18–25
20–22,
24–28
I/O
PORT B, PINS 0–7:
An 8-bit data output latch/buffer and an 8-
bit data input buffer.
V
CC
D
7–0
26
29
SYSTEM POWER:
a
5V Power Supply.
27–34
30–33,
35–38
I/O
DATA BUS:
Bi-directional, tri-state data bus lines, connected to
system data bus.
RESET
35
39
I
RESET:
A high on this input clears the control register and all
ports are set to the input mode.
WR
36
40
I
WRITE CONTROL:
This input is low during CPU write
operations.
PA
7–4
37–40
41–44
I/O
PORT A, PINS 4–7:
Upper nibble of an 8-bit data output latch/
buffer and an 8-bit data input latch.
NC
1, 12,
23, 34
No Connect
2
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